.. ************************************************** * * * Automatically generated file, do not edit! * * * ************************************************** .. _amdgpu_synid_gfx950_addr_c8b8d4: addr ---- *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_addr_f2b449: addr ---- *Size:* 2 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_data_be4895: data ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data_9ad749: data ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data_cfb402: data ---- Instruction input. *Size:* 3 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data_848ff7: data ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data0_be4895: data0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data0_9ad749: data0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data0_cfb402: data0 ----- Instruction input. *Size:* 3 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data0_848ff7: data0 ----- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data1_be4895: data1 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data1_9ad749: data1 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_literal_ad4155: literal ------- *Size:* 1 dword. *Operands:* :ref:`simm16` .. _amdgpu_synid_gfx950_literal_6f0844: literal ------- A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. The value is converted to *f32* as described :ref:`here`. .. _amdgpu_synid_gfx950_literal_a3e80c: literal ------- An :ref:`integer_number` or an :ref:`absolute_expression`. The value is truncated to 32 bits. .. _amdgpu_synid_gfx950_saddr_13d69a: saddr ----- *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_saddr_ce8216: saddr ----- *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sbase_010ce0: sbase ----- A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride. *Size:* 4 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sbase_044055: sbase ----- A 64-bit base address for scalar memory operations. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sbase_0cd545: sbase ----- This operand is ignored by H/W and :ref:`flat_scratch` is supplied instead. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_scale_src0: scale_src0 ---------- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_scale_src1: scale_src1 ---------- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_sdata_aefe00: sdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_eb6f2a: sdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_c6aec1: sdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 4 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_94342d: sdata ----- Instruction output. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_d725ab: sdata ----- Instruction output. *Size:* 1 dword. *Operands:* :ref:`simm8` .. _amdgpu_synid_gfx950_sdata_3bc700: sdata ----- Instruction output. *Size:* 16 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_718cc4: sdata ----- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_0804b1: sdata ----- Instruction output. *Size:* 4 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_362c37: sdata ----- Instruction output. *Size:* 8 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdst_02b357: sdst ---- *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec` .. _amdgpu_synid_gfx950_sdst_3bec61: sdst ---- Instruction output. *Size:* 1 dword if wavefront size is 32, otherwise 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdst_1db612: sdst ---- Instruction output. *Size:* 1 dword if wavefront size is 32, otherwise 2 dwords. *Operands:* :ref:`vcc` .. _amdgpu_synid_gfx950_sdst_94342d: sdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdst_06b266: sdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec` .. _amdgpu_synid_gfx950_sdst_718cc4: sdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdst_a319e6: sdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec` .. _amdgpu_synid_gfx950_simm16_ad4155: simm16 ------ *Size:* 1 dword. *Operands:* :ref:`simm16` .. _amdgpu_synid_gfx950_simm16_2f6714: simm16 ------ A 16-bit message code. The bits of this operand have the following meaning: ============ =============================== =============== Bits Description Value Range ============ =============================== =============== 3:0 Message *type*. 0..15 6:4 Optional *operation*. 0..7 7:7 Unused. \- 9:8 Optional *stream*. 0..3 15:10 Unused. \- ============ =============================== =============== This operand may be specified as one of the following: * An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..0xFFFF. * A *sendmsg* value described below. ==================================== ==================================================== Sendmsg Value Syntax Description ==================================== ==================================================== sendmsg(<*type*>) A message identified by its *type*. sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*. sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation* with a stream *id*. ==================================== ==================================================== *Type* may be specified using message *name* or message *id*. *Op* may be specified using operation *name* or operation *id*. Stream *id* is an integer in the range 0..3. Numeric values may be specified as positive :ref:`integer numbers` or :ref:`absolute expressions`. Each message type supports specific operations: ====================== ========== ============================== ============ ========== Message name Message Id Supported Operations Operation Id Stream Id ====================== ========== ============================== ============ ========== MSG_INTERRUPT 1 \- \- \- MSG_GS 2 GS_OP_CUT 1 Optional \ GS_OP_EMIT 2 Optional \ GS_OP_EMIT_CUT 3 Optional MSG_GS_DONE 3 GS_OP_NOP 0 \- \ GS_OP_CUT 1 Optional \ GS_OP_EMIT 2 Optional \ GS_OP_EMIT_CUT 3 Optional MSG_SAVEWAVE 4 \- \- \- MSG_STALL_WAVE_GEN 5 \- \- \- MSG_HALT_WAVES 6 \- \- \- MSG_ORDERED_PS_DONE 7 \- \- \- MSG_EARLY_PRIM_DEALLOC 8 \- \- \- MSG_GS_ALLOC_REQ 9 \- \- \- MSG_GET_DOORBELL 10 \- \- \- MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \- \ SYSMSG_OP_REG_RD 2 \- \ SYSMSG_OP_TTRACE_PC 4 \- ====================== ========== ============================== ============ ========== *Sendmsg* arguments are validated depending on how *type* value is specified: * If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above. * If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table). Examples: .. parsed-literal:: // numeric message code msg = 0x10 s_sendmsg 0x12 s_sendmsg msg + 2 // sendmsg with strict arguments validation s_sendmsg sendmsg(MSG_INTERRUPT) s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT) s_sendmsg sendmsg(MSG_GS, 2) s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1) s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC) s_sendmsg sendmsg(MSG_GET_DOORBELL) // sendmsg with validation of value range only msg = 2 op = 3 stream = 1 s_sendmsg sendmsg(msg, op, stream) s_sendmsg sendmsg(2, GS_OP_CUT) .. _amdgpu_synid_gfx950_simm16_dff4f4: simm16 ------ A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. This operand may be specified as one of the following: * An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..32767. * A :ref:`symbol` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. Examples: .. parsed-literal:: offset = 30 label_1: label_2 = . + 4 s_branch 32 s_branch offset + 2 s_branch label_1 s_branch label_2 s_branch label_3 s_branch label_4 label_3 = label_2 + 4 label_4: .. _amdgpu_synid_gfx950_simm16_de962b: simm16 ------ Bits of a hardware register being accessed. The bits of this operand have the following meaning: ======= ===================== ============ Bits Description Value Range ======= ===================== ============ 5:0 Register *id*. 0..63 10:6 First bit *offset*. 0..31 15:11 *Size* in bits. 1..32 ======= ===================== ============ This operand may be specified as one of the following: * An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..0xFFFF. * An *hwreg* value described below. ==================================== ============================================================================ Hwreg Value Syntax Description ==================================== ============================================================================ hwreg({0..63}) All bits of a register indicated by its *id*. hwreg(<*name*>) All bits of a register indicated by its *name*. hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*. hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*. ==================================== ============================================================================ Numeric values may be specified as positive :ref:`integer numbers` or :ref:`absolute expressions`. Defined register *names* include: =================== ========================================== Name Description =================== ========================================== HW_REG_MODE Shader writeable mode bits. HW_REG_STATUS Shader read-only status. HW_REG_TRAPSTS Trap status. HW_REG_HW_ID Id of wave, simd, compute unit, etc. HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation. HW_REG_LDS_ALLOC Per-wave LDS allocation. HW_REG_IB_STS Counters of outstanding instructions. HW_REG_SH_MEM_BASES Memory aperture. HW_REG_TBA_LO tba_lo register. HW_REG_TBA_HI tba_hi register. HW_REG_TMA_LO tma_lo register. HW_REG_TMA_HI tma_hi register. =================== ========================================== Examples: .. parsed-literal:: reg = 1 offset = 2 size = 4 hwreg_enc = reg | (offset << 6) | ((size - 1) << 11) s_getreg_b32 s2, 0x1881 s_getreg_b32 s2, hwreg_enc // the same as above s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above s_getreg_b32 s2, hwreg(15) s_getreg_b32 s2, hwreg(51, 1, 31) s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) .. _amdgpu_synid_gfx950_simm16_6d9906: simm16 ------ Counts of outstanding instructions to wait for. The bits of this operand have the following meaning: ========== ========= ================================================ ============ High Bits Low Bits Description Value Range ========== ========= ================================================ ============ 15:14 3:0 VM_CNT: vector memory operations count. 0..63 \- 6:4 EXP_CNT: export count. 0..7 \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15 ========== ========= ================================================ ============ This operand may be specified as one of the following: * An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..0xFFFF. * A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below. ====================== ====================================================================== Syntax Description ====================== ====================================================================== vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value. expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value. lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value). expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value). lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). ====================== ====================================================================== These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators. *N* is either an :ref:`integer number` or an :ref:`absolute expression`. Examples: .. parsed-literal:: vm_cnt = 1 exp_cnt = 2 lgkm_cnt = 3 cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8) s_waitcnt cnt s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above s_waitcnt vmcnt(1) s_waitcnt expcnt(2) lgkmcnt(3) s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3) s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2) .. _amdgpu_synid_gfx950_soffset_1189ef: soffset ------- An offset added to the base address to get memory address. * If offset is specified as a register, it supplies an unsigned byte offset. * If offset is specified as a 21-bit immediate, it supplies a signed byte offset. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0` .. _amdgpu_synid_gfx950_soffset_8aa27a: soffset ------- An unsigned 20-bit offset added to the base address to get memory address. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0` .. _amdgpu_synid_gfx950_soffset_d856a0: soffset ------- An unsigned byte offset. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src0_1027ca: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`a` .. _amdgpu_synid_gfx950_src0_6802ce: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_src0_be4895: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src0_516946: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`lds_direct` .. _amdgpu_synid_gfx950_src0_14b47a: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src0_0f0007: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_src0_168f33: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`fconst` .. _amdgpu_synid_gfx950_src0_06ee74: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_src0_9ad749: src0 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src0_e30a18: src0 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src0_62f8c2: src0 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_src0_848ff7: src0 ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src0_ca334d: src0 ---- Instruction input. *Size:* 8 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src0_1d4114: src0 ---- attr0.x through attr63.w, parameter attribute and channel to be interpolated .. _amdgpu_synid_gfx950_src1_43aa79: src1 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0` .. _amdgpu_synid_gfx950_src1_be4895: src1 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src1_14b47a: src1 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src1_d52854: src1 ---- Instruction input. *Size:* 16 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_src1_9ad749: src1 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src1_e30a18: src1 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src1_848ff7: src1 ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src1_ca334d: src1 ---- Instruction input. *Size:* 8 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src2_6802ce: src2 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_src2_14b47a: src2 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_14f1c8: src2 ---- Instruction input. *Size:* 16 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_1ff383: src2 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_e30a18: src2 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_a90bd6: src2 ---- Instruction input. *Size:* 32 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_e016a1: src2 ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_src2_ca14ce: src2 ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_f36021: src2 ---- Instruction input. *Size:* 8 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_srsrc: srsrc ----- Buffer resource constant which defines the address and characteristics of the buffer in memory. *Size:* 4 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_ssrc0_595c25: ssrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_ssrc0_eecc17: ssrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_ssrc0_e9f591: ssrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_ssrc0_1ce478: ssrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_ssrc0_83ef5a: ssrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_ssrc1_5c7b50: ssrc1 ----- Instruction input. *Size:* 1 dword. *Operands:* .. _amdgpu_synid_gfx950_ssrc1_eecc17: ssrc1 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_ssrc1_1ce478: ssrc1 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_ssrc1_83ef5a: ssrc1 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_vaddr: vaddr ----- This is an optional operand which may specify offset and/or index. *Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen` and :ref:`idxen`: * If only :ref:`idxen` is specified, this operand supplies an index. Size is 1 dword. * If only :ref:`offen` is specified, this operand supplies an offset. Size is 1 dword. * If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords. * If none of these modifiers are specified, this operand must be set to :ref:`off`. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vcc: vcc --- Vector condition code. *Size:* 1 dword. *Operands:* :ref:`vcc` .. _amdgpu_synid_gfx950_vdata_2a60db: vdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_2d0375: vdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_8e9b87: vdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_fa7dbd: vdata ----- Instruction output. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_0f48d1: vdata ----- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_260aca: vdata ----- Instruction output. *Size:* 3 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_180bef: vdata ----- Instruction output. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_c8ee02: vdst ---- Data returned by a 32-bit atomic flat instruction. This is an optional operand. It must be used if and only if :ref:`glc` is specified. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_ef6c94: vdst ---- Data returned by a 64-bit atomic flat instruction. This is an optional operand. It must be used if and only if :ref:`glc` is specified. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_78dd0a: vdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`a` .. _amdgpu_synid_gfx950_vdst_59204c: vdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`ttmp` .. _amdgpu_synid_gfx950_vdst_89680f: vdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_fa7dbd: vdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_5f7812: vdst ---- Instruction output. *Size:* 16 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_d6f4bd: vdst ---- Instruction output. *Size:* 16 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_bdb32f: vdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_0f48d1: vdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_260aca: vdst ---- Instruction output. *Size:* 3 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_2eda77: vdst ---- Instruction output. *Size:* 32 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_8c77d4: vdst ---- Instruction output. *Size:* 32 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_69a144: vdst ---- Instruction output. *Size:* 4 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_180bef: vdst ---- Instruction output. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_363335: vdst ---- Instruction output. *Size:* 6 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_c8d317: vdst ---- Instruction output. *Size:* 8 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vsrc0_1027ca: vsrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`a` .. _amdgpu_synid_gfx950_vsrc0_6802ce: vsrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vsrc0_14b47a: vsrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_vsrc0_0f0007: vsrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_vsrc0_fd235e: vsrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vsrc0_e30a18: vsrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_vsrc1_6802ce: vsrc1 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vsrc1_14b47a: vsrc1 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_vsrc1_fd235e: vsrc1 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`