|
| enum | llvm::AArch64CC::CondCode {
llvm::AArch64CC::EQ = 0x0
, llvm::AArch64CC::NE = 0x1
, llvm::AArch64CC::HS = 0x2
, llvm::AArch64CC::LO = 0x3
,
llvm::AArch64CC::MI = 0x4
, llvm::AArch64CC::PL = 0x5
, llvm::AArch64CC::VS = 0x6
, llvm::AArch64CC::VC = 0x7
,
llvm::AArch64CC::HI = 0x8
, llvm::AArch64CC::LS = 0x9
, llvm::AArch64CC::GE = 0xa
, llvm::AArch64CC::LT = 0xb
,
llvm::AArch64CC::GT = 0xc
, llvm::AArch64CC::LE = 0xd
, llvm::AArch64CC::AL = 0xe
, llvm::AArch64CC::NV = 0xf
,
llvm::AArch64CC::Invalid
, llvm::AArch64CC::ANY_ACTIVE = NE
, llvm::AArch64CC::FIRST_ACTIVE = MI
, llvm::AArch64CC::LAST_ACTIVE = LO
,
llvm::AArch64CC::NONE_ACTIVE = EQ
} |
| enum class | llvm::TailFoldingOpts : uint8_t {
llvm::Disabled = 0x00
, llvm::Simple = 0x01
, llvm::Reductions = 0x02
, llvm::Recurrences = 0x04
,
llvm::Reverse = 0x08
, llvm::All = Reductions | Recurrences | Simple | Reverse
} |
| | An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Loops containing reductions Recurrences: Loops with first-order recurrences, i.e. More...
|
| enum | llvm::AArch64SME::ToggleCondition : unsigned { llvm::AArch64SME::Always
, llvm::AArch64SME::IfCallerIsStreaming
, llvm::AArch64SME::IfCallerIsNonStreaming
} |
| enum | llvm::AArch64SE::ShiftExtSpecifiers {
llvm::AArch64SE::Invalid = -1
, llvm::AArch64SE::LSL
, llvm::AArch64SE::MSL
, llvm::AArch64SE::LSR
,
llvm::AArch64SE::ASR
, llvm::AArch64SE::ROR
, llvm::AArch64SE::UXTB
, llvm::AArch64SE::UXTH
,
llvm::AArch64SE::UXTW
, llvm::AArch64SE::UXTX
, llvm::AArch64SE::SXTB
, llvm::AArch64SE::SXTH
,
llvm::AArch64SE::SXTW
, llvm::AArch64SE::SXTX
} |
| enum | llvm::AArch64Layout::VectorLayout {
llvm::AArch64Layout::Invalid = -1
, llvm::AArch64Layout::VL_8B
, llvm::AArch64Layout::VL_4H
, llvm::AArch64Layout::VL_2S
,
llvm::AArch64Layout::VL_1D
, llvm::AArch64Layout::VL_16B
, llvm::AArch64Layout::VL_8H
, llvm::AArch64Layout::VL_4S
,
llvm::AArch64Layout::VL_2D
, llvm::AArch64Layout::VL_B
, llvm::AArch64Layout::VL_H
, llvm::AArch64Layout::VL_S
,
llvm::AArch64Layout::VL_D
} |
| enum | llvm::AArch64II::TOF {
llvm::AArch64II::MO_NO_FLAG
, llvm::AArch64II::MO_FRAGMENT = 0x7
, llvm::AArch64II::MO_PAGE = 1
, llvm::AArch64II::MO_PAGEOFF = 2
,
llvm::AArch64II::MO_G3 = 3
, llvm::AArch64II::MO_G2 = 4
, llvm::AArch64II::MO_G1 = 5
, llvm::AArch64II::MO_G0 = 6
,
llvm::AArch64II::MO_HI12 = 7
, llvm::AArch64II::MO_COFFSTUB = 0x8
, llvm::AArch64II::MO_GOT = 0x10
, llvm::AArch64II::MO_NC = 0x20
,
llvm::AArch64II::MO_TLS = 0x40
, llvm::AArch64II::MO_DLLIMPORT = 0x80
, llvm::AArch64II::MO_S = 0x100
, llvm::AArch64II::MO_PREL = 0x200
,
llvm::AArch64II::MO_TAGGED = 0x400
, llvm::AArch64II::MO_ARM64EC_CALLMANGLE = 0x800
} |
| | Target Operand Flag enum. More...
|
| enum | llvm::AArch64PACKey::ID : uint8_t {
llvm::AArch64PACKey::IA = 0
, llvm::AArch64PACKey::IB = 1
, llvm::AArch64PACKey::DA = 2
, llvm::AArch64PACKey::DB = 3
,
llvm::AArch64PACKey::LAST = DB
} |
|
| static MCRegister | llvm::getWRegFromXReg (MCRegister Reg) |
| static MCRegister | llvm::getXRegFromWReg (MCRegister Reg) |
| static MCRegister | llvm::getXRegFromXRegTuple (MCRegister RegTuple) |
| static MCRegister | llvm::getBRegFromDReg (MCRegister Reg) |
| static MCRegister | llvm::getDRegFromBReg (MCRegister Reg) |
| static bool | llvm::atomicBarrierDroppedOnZero (unsigned Opcode) |
| unsigned | llvm::CheckFixedPointOperandConstant (APFloat &FVal, unsigned RegWidth, bool isReciprocal) |
| static const char * | llvm::AArch64CC::getCondCodeName (CondCode Code) |
| static CondCode | llvm::AArch64CC::getInvertedCondCode (CondCode Code) |
| static CondCode | llvm::AArch64CC::getSwappedCondition (CondCode CC) |
| | getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).
|
| static unsigned | llvm::AArch64CC::getNZCVToSatisfyCondCode (CondCode Code) |
| | Given a condition code, return NZCV flags that would satisfy that condition.
|
| static bool | llvm::AArch64CC::isValidCBCond (AArch64CC::CondCode Code) |
| | True, if a given condition code can be used in a fused compare-and-branch instructions, false otherwise.
|
| unsigned | llvm::getNumElementsFromSVEPredPattern (unsigned Pattern) |
| | Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
|
| std::optional< unsigned > | llvm::getSVEPredPatternFromNumElements (unsigned MinNumElts) |
| | Return specific VL predicate pattern based on the number of elements.
|
| | llvm::LLVM_DECLARE_ENUM_AS_BITMASK (TailFoldingOpts,(long) TailFoldingOpts::Reverse) |
| static const char * | llvm::AArch64VectorLayoutToString (AArch64Layout::VectorLayout Layout) |
| static AArch64Layout::VectorLayout | llvm::AArch64StringToVectorLayout (StringRef LayoutStr) |
| uint32_t | llvm::AArch64SysReg::parseGenericRegister (StringRef Name) |
| std::string | llvm::AArch64SysReg::genericRegisterString (uint32_t Bits) |
| static StringRef | llvm::AArch64PACKeyIDToString (AArch64PACKey::ID KeyID) |
| | Return 2-letter identifier string for numeric key ID.
|
| static std::optional< AArch64PACKey::ID > | llvm::AArch64StringToPACKeyID (StringRef Name) |
| | Return numeric key ID for 2-letter identifier string.
|
| static unsigned | llvm::getBTIHintNum (bool CallTarget, bool JumpTarget) |
1.14.0