#include "HexagonInstrInfo.h"
#include "HexagonFrameLowering.h"
#include "HexagonHazardRecognizer.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/DFAPacketizer.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <cctype>
#include <cstdint>
#include <cstring>
#include <iterator>
#include <optional>
#include <string>
#include <utility>
#include "HexagonDepTimingClasses.h"
#include "HexagonGenDFAPacketizer.inc"
#include "HexagonGenInstrInfo.inc"

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::HexagonFUnits

Macros
#define	DEBUG_TYPE "hexagon-instrinfo"
#define	GET_INSTRINFO_CTOR_DTOR
#define	GET_INSTRMAP_INFO

Functions
bool	llvm::HexagonFUnits::isSlot0Only (unsigned units)
static bool	isIntRegForSubInst (Register Reg)
static bool	isDblRegForSubInst (Register Reg, const HexagonRegisterInfo &HRI)
static unsigned	nonDbgMICount (MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE)
	Calculate number of instructions excluding the debug instructions.
static void	parseOperands (const MachineInstr &MI, SmallVectorImpl< Register > &Defs, SmallVectorImpl< Register > &Uses)
	Gather register def/uses from MI.
static bool	isDuplexPairMatch (unsigned Ga, unsigned Gb)
static void	getLiveInRegsAt (LivePhysRegs &Regs, const MachineInstr &MI)
static void	getLiveOutRegsAt (LivePhysRegs &Regs, const MachineInstr &MI)

Variables
cl::opt< bool >	ScheduleInlineAsm ("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))
static cl::opt< bool >	EnableBranchPrediction ("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
static cl::opt< bool >	DisableNVSchedule ("disable-hexagon-nv-schedule", cl::Hidden, cl::desc("Disable schedule adjustment for new value stores."))
static cl::opt< bool >	EnableTimingClassLatency ("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))
static cl::opt< bool >	EnableALUForwarding ("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
static cl::opt< bool >	EnableACCForwarding ("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
static cl::opt< bool >	BranchRelaxAsmLarge ("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::desc("branch relax asm"))
static cl::opt< bool >	UseDFAHazardRec ("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::desc("Use the DFA based hazard recognizer."))
const int	Hexagon_MEMW_OFFSET_MAX = 4095
	Constants for Hexagon instructions.
const int	Hexagon_MEMW_OFFSET_MIN = -4096
const int	Hexagon_MEMD_OFFSET_MAX = 8191
const int	Hexagon_MEMD_OFFSET_MIN = -8192
const int	Hexagon_MEMH_OFFSET_MAX = 2047
const int	Hexagon_MEMH_OFFSET_MIN = -2048
const int	Hexagon_MEMB_OFFSET_MAX = 1023
const int	Hexagon_MEMB_OFFSET_MIN = -1024
const int	Hexagon_ADDI_OFFSET_MAX = 32767
const int	Hexagon_ADDI_OFFSET_MIN = -32768

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "hexagon-instrinfo"

Definition at line 66 of file HexagonInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 68 of file HexagonInstrInfo.cpp.

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

Definition at line 69 of file HexagonInstrInfo.cpp.

Function Documentation

◆ getLiveInRegsAt()

void getLiveInRegsAt	(	LivePhysRegs &	Regs,
		const MachineInstr &	MI )

static

Definition at line 841 of file HexagonInstrInfo.cpp.

References llvm::LivePhysRegs::addLiveIns(), B(), llvm::SmallVectorImpl< T >::clear(), E(), I, MI, and llvm::LivePhysRegs::stepForward().

Referenced by llvm::HexagonInstrInfo::copyPhysReg(), and llvm::HexagonInstrInfo::expandPostRAPseudo().

◆ getLiveOutRegsAt()

void getLiveOutRegsAt	(	LivePhysRegs &	Regs,
		const MachineInstr &	MI )

static

Definition at line 852 of file HexagonInstrInfo.cpp.

References llvm::LivePhysRegs::addLiveOuts(), B(), E(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), I, MI, and llvm::LivePhysRegs::stepBackward().

Referenced by llvm::HexagonInstrInfo::expandPostRAPseudo().

◆ isDblRegForSubInst()

bool isDblRegForSubInst	(	Register	Reg,
		const HexagonRegisterInfo &	HRI )

static

Definition at line 136 of file HexagonInstrInfo.cpp.

References isIntRegForSubInst(), and Reg.

Referenced by llvm::HexagonInstrInfo::getDuplexCandidateGroup().

◆ isDuplexPairMatch()

bool isDuplexPairMatch	(	unsigned	Ga,
		unsigned	Gb )

static

Definition at line 259 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_Compound, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, and llvm::HexagonII::HSIG_S2.

Referenced by llvm::HexagonInstrInfo::isDuplexPair(), llvm::HexagonMCInstrInfo::isDuplexPair(), and llvm::HexagonMCInstrInfo::isOrderedDuplexPair().

◆ isIntRegForSubInst()

bool isIntRegForSubInst ( Register Reg )

static

Definition at line 131 of file HexagonInstrInfo.cpp.

References Reg.

Referenced by llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), and isDblRegForSubInst().

◆ nonDbgMICount()

unsigned nonDbgMICount	(	MachineBasicBlock::const_instr_iterator	MIB,
		MachineBasicBlock::const_instr_iterator	MIE )

static

Calculate number of instructions excluding the debug instructions.

Definition at line 142 of file HexagonInstrInfo.cpp.

References llvm::Count.

Referenced by llvm::HexagonInstrInfo::nonDbgBBSize(), and llvm::HexagonInstrInfo::nonDbgBundleSize().

◆ parseOperands()

void parseOperands	(	const MachineInstr &	MI,
		SmallVectorImpl< Register > &	Defs,
		SmallVectorImpl< Register > &	Uses )

inlinestatic

Gather register def/uses from MI.

This treats possible (predicated) defs as actually happening ones (conservatively).

Definition at line 237 of file HexagonInstrInfo.cpp.

References llvm::SmallVectorImpl< T >::clear(), MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, and Uses.

Referenced by llvm::HexagonInstrInfo::isDependent().

Variable Documentation

◆ BranchRelaxAsmLarge

cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::desc("branch relax asm"))	(	"branch-relax-asm-large"	,
		cl::init(true)	,
		cl::Hidden	,
		cl::desc("branch relax asm")	)

static

Referenced by llvm::HexagonInstrInfo::getSize().

◆ DisableNVSchedule

cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::desc("Disable schedule adjustment for new value stores."))	(	"disable-hexagon-nv-schedule"	,
		cl::Hidden	,
		cl::desc("Disable schedule adjustment for new value stores.")	)

static

Referenced by llvm::HexagonInstrInfo::canExecuteInBundle().

◆ EnableACCForwarding

cl::opt< bool > EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))	(	"enable-acc-forwarding"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Enable vec acc forwarding")	)

static

Referenced by llvm::HexagonInstrInfo::isVecUsableNextPacket().

◆ EnableALUForwarding

cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))	(	"enable-alu-forwarding"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Enable vec alu forwarding")	)

static

Referenced by llvm::HexagonInstrInfo::isVecUsableNextPacket().

◆ EnableBranchPrediction

cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))	(	"hexagon-enable-branch-prediction"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Enable branch prediction")	)

static

Referenced by llvm::HexagonInstrInfo::invertAndChangeJumpTarget().

◆ EnableTimingClassLatency

cl::opt< bool > EnableTimingClassLatency("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))	(	"enable-timing-class-latency"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc("Enable timing class latency")	)

static

◆ Hexagon_ADDI_OFFSET_MAX

const int Hexagon_ADDI_OFFSET_MAX = 32767

Definition at line 114 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_ADDI_OFFSET_MIN

const int Hexagon_ADDI_OFFSET_MIN = -32768

Definition at line 115 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMB_OFFSET_MAX

const int Hexagon_MEMB_OFFSET_MAX = 1023

Definition at line 112 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMB_OFFSET_MIN

const int Hexagon_MEMB_OFFSET_MIN = -1024

Definition at line 113 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMD_OFFSET_MAX

const int Hexagon_MEMD_OFFSET_MAX = 8191

Definition at line 108 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMD_OFFSET_MIN

const int Hexagon_MEMD_OFFSET_MIN = -8192

Definition at line 109 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMH_OFFSET_MAX

const int Hexagon_MEMH_OFFSET_MAX = 2047

Definition at line 110 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMH_OFFSET_MIN

const int Hexagon_MEMH_OFFSET_MIN = -2048

Definition at line 111 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMW_OFFSET_MAX

const int Hexagon_MEMW_OFFSET_MAX = 4095

Constants for Hexagon instructions.

Definition at line 106 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMW_OFFSET_MIN

const int Hexagon_MEMW_OFFSET_MIN = -4096

Definition at line 107 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ ScheduleInlineAsm

cl::opt< bool > ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))	(	"hexagon-sched-inline-asm"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary.")	)

Referenced by llvm::HexagonInstrInfo::isSchedulingBoundary(), and llvm::HexagonPacketizerList::isSoloInstruction().

◆ UseDFAHazardRec

cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::desc("Use the DFA based hazard recognizer."))	(	"dfa-hazard-rec"	,
		cl::init(true)	,
		cl::Hidden	,
		cl::desc("Use the DFA based hazard recognizer.")	)

static

Referenced by llvm::HexagonInstrInfo::CreateTargetPostRAHazardRecognizer().

Namespaces

Macros

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GET_INSTRINFO_CTOR_DTOR

◆ GET_INSTRMAP_INFO

Function Documentation

◆ getLiveInRegsAt()

◆ getLiveOutRegsAt()

◆ isDblRegForSubInst()

◆ isDuplexPairMatch()

◆ isIntRegForSubInst()

◆ nonDbgMICount()

◆ parseOperands()

Variable Documentation

◆ BranchRelaxAsmLarge

◆ DisableNVSchedule

◆ EnableACCForwarding

◆ EnableALUForwarding

◆ EnableBranchPrediction

◆ EnableTimingClassLatency

◆ Hexagon_ADDI_OFFSET_MAX

◆ Hexagon_ADDI_OFFSET_MIN

◆ Hexagon_MEMB_OFFSET_MAX

◆ Hexagon_MEMB_OFFSET_MIN

◆ Hexagon_MEMD_OFFSET_MAX

◆ Hexagon_MEMD_OFFSET_MIN

◆ Hexagon_MEMH_OFFSET_MAX

◆ Hexagon_MEMH_OFFSET_MIN

◆ Hexagon_MEMW_OFFSET_MAX

◆ Hexagon_MEMW_OFFSET_MIN

◆ ScheduleInlineAsm

◆ UseDFAHazardRec