85 if (&Subtarget == &NewSubtarget)
88 Names2InstrOpCodes.clear();
90 Names2RegMasks.clear();
91 Names2SubRegIndices.clear();
92 Names2TargetIndices.clear();
93 Names2DirectTargetFlags.clear();
94 Names2BitmaskTargetFlags.clear();
95 Names2MMOTargetFlags.clear();
97 initNames2RegClasses();
101void PerTargetMIParsingState::initNames2Regs() {
102 if (!Names2Regs.empty())
106 Names2Regs.insert(std::make_pair(
"noreg", 0));
108 assert(
TRI &&
"Expected target register info");
110 for (
unsigned I = 0, E =
TRI->getNumRegs();
I < E; ++
I) {
115 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
122 auto RegInfo = Names2Regs.find(
RegName);
123 if (RegInfo == Names2Regs.end())
125 Reg = RegInfo->getValue();
131 const auto *
TRI = Subtarget.getRegisterInfo();
132 std::optional<uint8_t> FV =
TRI->getVRegFlagValue(FlagName);
139void PerTargetMIParsingState::initNames2InstrOpCodes() {
140 if (!Names2InstrOpCodes.
empty())
143 assert(
TII &&
"Expected target instruction info");
144 for (
unsigned I = 0, E =
TII->getNumOpcodes();
I < E; ++
I)
150 initNames2InstrOpCodes();
151 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
152 if (InstrInfo == Names2InstrOpCodes.end())
154 OpCode = InstrInfo->getValue();
158void PerTargetMIParsingState::initNames2RegMasks() {
159 if (!Names2RegMasks.
empty())
162 assert(
TRI &&
"Expected target register info");
166 for (
size_t I = 0, E = RegMasks.
size();
I < E; ++
I)
168 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
172 initNames2RegMasks();
173 auto RegMaskInfo = Names2RegMasks.find(Identifier);
174 if (RegMaskInfo == Names2RegMasks.end())
176 return RegMaskInfo->getValue();
179void PerTargetMIParsingState::initNames2SubRegIndices() {
180 if (!Names2SubRegIndices.
empty())
183 for (
unsigned I = 1, E =
TRI->getNumSubRegIndices();
I < E; ++
I)
184 Names2SubRegIndices.
insert(
185 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
189 initNames2SubRegIndices();
190 auto SubRegInfo = Names2SubRegIndices.find(Name);
191 if (SubRegInfo == Names2SubRegIndices.end())
193 return SubRegInfo->getValue();
196void PerTargetMIParsingState::initNames2TargetIndices() {
197 if (!Names2TargetIndices.
empty())
200 assert(
TII &&
"Expected target instruction info");
201 auto Indices =
TII->getSerializableTargetIndices();
202 for (
const auto &
I : Indices)
207 initNames2TargetIndices();
208 auto IndexInfo = Names2TargetIndices.find(Name);
209 if (IndexInfo == Names2TargetIndices.end())
211 Index = IndexInfo->second;
215void PerTargetMIParsingState::initNames2DirectTargetFlags() {
216 if (!Names2DirectTargetFlags.
empty())
220 assert(
TII &&
"Expected target instruction info");
221 auto Flags =
TII->getSerializableDirectMachineOperandTargetFlags();
222 for (
const auto &
I : Flags)
223 Names2DirectTargetFlags.
insert(
229 initNames2DirectTargetFlags();
230 auto FlagInfo = Names2DirectTargetFlags.find(Name);
231 if (FlagInfo == Names2DirectTargetFlags.end())
233 Flag = FlagInfo->second;
237void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
238 if (!Names2BitmaskTargetFlags.
empty())
242 assert(
TII &&
"Expected target instruction info");
243 auto Flags =
TII->getSerializableBitmaskMachineOperandTargetFlags();
244 for (
const auto &
I : Flags)
245 Names2BitmaskTargetFlags.
insert(
251 initNames2BitmaskTargetFlags();
252 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
253 if (FlagInfo == Names2BitmaskTargetFlags.end())
255 Flag = FlagInfo->second;
259void PerTargetMIParsingState::initNames2MMOTargetFlags() {
260 if (!Names2MMOTargetFlags.
empty())
264 assert(
TII &&
"Expected target instruction info");
265 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
266 for (
const auto &
I : Flags)
272 initNames2MMOTargetFlags();
273 auto FlagInfo = Names2MMOTargetFlags.find(Name);
274 if (FlagInfo == Names2MMOTargetFlags.end())
276 Flag = FlagInfo->second;
280void PerTargetMIParsingState::initNames2RegClasses() {
281 if (!Names2RegClasses.
empty())
285 for (
unsigned I = 0, E =
TRI->getNumRegClasses();
I < E; ++
I) {
286 const auto *RC =
TRI->getRegClass(
I);
292void PerTargetMIParsingState::initNames2RegBanks() {
293 if (!Names2RegBanks.empty())
296 const RegisterBankInfo *RBI = Subtarget.getRegBankInfo();
304 Names2RegBanks.insert(
305 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank));
311 auto RegClassInfo = Names2RegClasses.find(Name);
312 if (RegClassInfo == Names2RegClasses.end())
314 return RegClassInfo->getValue();
318 auto RegBankInfo = Names2RegBanks.find(Name);
319 if (RegBankInfo == Names2RegBanks.end())
321 return RegBankInfo->getValue();
335 I.first->second = Info;
337 return *
I.first->second;
346 Info->
VReg =
MF.getRegInfo().createIncompleteVirtualRegister(
RegName);
347 I.first->second = Info;
349 return *
I.first->second;
357 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
365 for (
const auto &Arg :
F.args())
367 for (
const auto &BB :
F) {
369 for (
const auto &
I : BB)
384struct ParsedMachineOperand {
388 std::optional<unsigned> TiedDefIdx;
392 std::optional<unsigned> &TiedDefIdx)
393 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
396 "Only used register operands can be tied");
403 StringRef
Source, CurrentSource;
406 PerFunctionMIParsingState &PFS;
408 DenseMap<unsigned, const BasicBlock *> Slots2BasicBlocks;
411 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
413 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
414 StringRef Source, SMRange SourceRange);
418 void lex(
unsigned SkipChar = 0);
423 bool error(
const Twine &Msg);
431 parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
432 bool parseBasicBlocks();
434 bool parseStandaloneMBB(MachineBasicBlock *&
MBB);
436 bool parseStandaloneVirtualRegister(VRegInfo *&Info);
438 bool parseStandaloneStackObject(
int &FI);
439 bool parseStandaloneMDNode(MDNode *&Node);
441 bool parseMDTuple(MDNode *&MD,
bool IsDistinct);
442 bool parseMDNodeVector(SmallVectorImpl<Metadata *> &Elts);
446 parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
447 bool parseBasicBlock(MachineBasicBlock &
MBB,
448 MachineBasicBlock *&AddFalthroughFrom);
449 bool parseBasicBlockLiveins(MachineBasicBlock &
MBB);
450 bool parseBasicBlockSuccessors(MachineBasicBlock &
MBB);
453 bool parseVirtualRegister(VRegInfo *&Info);
454 bool parseNamedVirtualRegister(VRegInfo *&Info);
455 bool parseRegister(
Register &
Reg, VRegInfo *&VRegInfo);
456 bool parseRegisterFlag(
RegState &Flags);
457 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
458 bool parseSubRegisterIndex(
unsigned &SubReg);
459 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
460 bool parseRegisterOperand(MachineOperand &Dest,
461 std::optional<unsigned> &TiedDefIdx,
463 bool parseImmediateOperand(MachineOperand &Dest);
464 bool parseSymbolicInlineAsmOperand(
unsigned OpIdx, MachineOperand &Dest);
469 bool parseTypedImmediateOperand(MachineOperand &Dest);
470 bool parseFPImmediateOperand(MachineOperand &Dest);
472 bool parseMBBOperand(MachineOperand &Dest);
473 bool parseStackFrameIndex(
int &FI);
474 bool parseStackObjectOperand(MachineOperand &Dest);
475 bool parseFixedStackFrameIndex(
int &FI);
476 bool parseFixedStackObjectOperand(MachineOperand &Dest);
478 bool parseGlobalAddressOperand(MachineOperand &Dest);
479 bool parseConstantPoolIndexOperand(MachineOperand &Dest);
480 bool parseSubRegisterIndexOperand(MachineOperand &Dest);
481 bool parseJumpTableIndexOperand(MachineOperand &Dest);
482 bool parseExternalSymbolOperand(MachineOperand &Dest);
483 bool parseMCSymbolOperand(MachineOperand &Dest);
485 bool parseDIExpression(MDNode *&Expr);
486 bool parseDILocation(MDNode *&Expr);
487 bool parseMetadataOperand(MachineOperand &Dest);
488 bool parseCFIOffset(
int &
Offset);
489 bool parseCFIUnsigned(
unsigned &
Value);
490 bool parseCFIRegister(
unsigned &
Reg);
492 bool parseCFIEscapeValues(std::string& Values);
493 bool parseCFIOperand(MachineOperand &Dest);
494 bool parseIRBlock(BasicBlock *&BB,
const Function &
F);
495 bool parseBlockAddressOperand(MachineOperand &Dest);
496 bool parseIntrinsicOperand(MachineOperand &Dest);
497 bool parsePredicateOperand(MachineOperand &Dest);
498 bool parseShuffleMaskOperand(MachineOperand &Dest);
499 bool parseTargetIndexOperand(MachineOperand &Dest);
500 bool parseDbgInstrRefOperand(MachineOperand &Dest);
501 bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
502 bool parseLaneMaskOperand(MachineOperand &Dest);
503 bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
504 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
505 MachineOperand &Dest,
506 std::optional<unsigned> &TiedDefIdx);
507 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
508 const unsigned OpIdx,
509 MachineOperand &Dest,
510 std::optional<unsigned> &TiedDefIdx);
511 bool parseOffset(int64_t &
Offset);
512 bool parseIRBlockAddressTaken(BasicBlock *&BB);
514 bool parseAddrspace(
unsigned &Addrspace);
515 bool parseSectionID(std::optional<MBBSectionID> &SID);
516 bool parseBBID(std::optional<UniqueBBID> &BBID);
517 bool parseCallFrameSize(
unsigned &CallFrameSize);
519 bool parseOperandsOffset(MachineOperand &
Op);
522 bool parseMemoryPseudoSourceValue(
const PseudoSourceValue *&PSV);
523 bool parseMachinePointerInfo(MachinePointerInfo &Dest);
526 bool parseMachineMemoryOperand(MachineMemOperand *&Dest);
527 bool parsePreOrPostInstrSymbol(MCSymbol *&Symbol);
528 bool parseHeapAllocMarker(MDNode *&Node);
529 bool parsePCSections(MDNode *&Node);
530 bool parseMMRA(MDNode *&Node);
532 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
533 MachineOperand &Dest,
const MIRFormatter &MF);
544 bool getUint64(uint64_t &Result);
560 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
562 bool assignRegisterTies(MachineInstr &
MI,
566 const MCInstrDesc &MCID);
569 const BasicBlock *getIRBlock(
unsigned Slot,
const Function &
F);
572 MCSymbol *getOrCreateMCSymbol(StringRef Name);
576 bool parseStringConstant(std::string &Result);
593 SourceRange(SourceRange), PFS(PFS) {}
595void MIParser::lex(
unsigned SkipChar) {
597 CurrentSource.substr(SkipChar), Token,
601bool MIParser::error(
const Twine &Msg) {
return error(Token.location(), Msg); }
621 assert(SourceRange.isValid() &&
"Invalid source range");
643 return "<unknown token>";
648 if (Token.isNot(TokenKind))
655 if (Token.isNot(TokenKind))
662bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
668 return error(
"Unknown Section ID");
671 const StringRef &S = Token.stringValue();
672 if (S ==
"Exception")
674 else if (S ==
"Cold")
677 return error(
"Unknown Section ID");
684bool MIParser::parseBBID(std::optional<UniqueBBID> &BBID) {
686 return error(
"expected 'bb_id'");
689 unsigned CloneID = 0;
692 auto Parts = S.
split(
'.');
693 if (Parts.first.getAsInteger(10, BaseID) ||
694 Parts.second.getAsInteger(10, CloneID))
695 return error(
"Unknown BB ID");
699 return error(
"Unknown BB ID");
704 return error(
"Unknown Clone ID");
708 return error(
"Unknown Clone ID");
712 BBID = {BaseID, CloneID};
717bool MIParser::parseCallFrameSize(
unsigned &CallFrameSize) {
722 return error(
"Unknown call frame size");
723 CallFrameSize =
Value;
730 std::optional<UniqueBBID> BBID;
739bool MIParser::parseBasicBlockDefinition(
745 auto Loc = Token.location();
746 auto Name = Token.stringValue();
748 bool MachineBlockAddressTaken =
false;
750 bool IsLandingPad =
false;
751 bool IsInlineAsmBrIndirectTarget =
false;
752 bool IsEHFuncletEntry =
false;
753 bool IsEHScopeEntry =
false;
754 std::optional<MBBSectionID> SectionID;
755 uint64_t Alignment = 0;
756 std::optional<UniqueBBID> BBID;
757 unsigned CallFrameSize = 0;
762 switch (Token.kind()) {
764 MachineBlockAddressTaken =
true;
768 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
776 IsInlineAsmBrIndirectTarget =
true;
780 IsEHFuncletEntry =
true;
784 IsEHScopeEntry =
true;
794 if (parseIRBlock(BB, MF.getFunction()))
799 if (parseSectionID(SectionID))
807 if (parseCallFrameSize(CallFrameSize))
822 MF.getFunction().getValueSymbolTable()->lookup(Name));
825 "' is not defined in the function '" +
828 auto *
MBB = MF.CreateMachineBasicBlock(BB, BBID);
830 bool WasInserted = MBBSlots.
insert(std::make_pair(
ID,
MBB)).second;
832 return error(
Loc,
Twine(
"redefinition of machine basic block with id #") +
836 if (MachineBlockAddressTaken)
838 if (AddressTakenIRBlock)
852bool MIParser::parseBasicBlockDefinitions(
858 if (Token.isErrorOrEOF())
859 return Token.isError();
861 return error(
"expected a basic block definition before instructions");
862 unsigned BraceDepth = 0;
864 if (parseBasicBlockDefinition(MBBSlots))
866 bool IsAfterNewline =
false;
870 Token.isErrorOrEOF())
873 return error(
"basic block definition should be located at the start of "
876 IsAfterNewline =
true;
879 IsAfterNewline =
false;
884 return error(
"extraneous closing brace ('}')");
890 if (!Token.isError() && BraceDepth)
891 return error(
"expected '}'");
892 }
while (!Token.isErrorOrEOF());
893 return Token.isError();
901 if (Token.isNewlineOrEOF())
905 return error(
"expected a named register");
907 if (parseNamedRegister(
Reg))
915 return error(
"expected a lane mask");
917 "Use correct get-function for lane mask");
920 return error(
"invalid lane mask value");
934 if (Token.isNewlineOrEOF())
938 return error(
"expected a machine basic block reference");
947 return error(
"expected an integer literal after '('");
981 bool ExplicitSuccessors =
false;
984 if (parseBasicBlockSuccessors(
MBB))
986 ExplicitSuccessors =
true;
988 if (parseBasicBlockLiveins(
MBB))
995 if (!Token.isNewlineOrEOF())
996 return error(
"expected line break at the end of a list");
1001 bool IsInBundle =
false;
1025 return error(
"nested instruction bundles are not allowed");
1034 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
1039 if (!ExplicitSuccessors) {
1046 if (IsFallthrough) {
1047 AddFalthroughFrom = &
MBB;
1056bool MIParser::parseBasicBlocks() {
1061 if (Token.isErrorOrEOF())
1062 return Token.isError();
1071 if (AddFalthroughFrom) {
1075 AddFalthroughFrom =
nullptr;
1077 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1090 while (Token.isRegister() || Token.isRegisterFlag()) {
1091 auto Loc = Token.location();
1092 std::optional<unsigned> TiedDefIdx;
1093 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1096 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1105 if (Token.isError() || parseInstruction(OpCode, Flags))
1118 auto Loc = Token.location();
1119 std::optional<unsigned> TiedDefIdx;
1120 if (parseMachineOperandAndTargetFlags(OpCode, Operands.
size(), MO, TiedDefIdx))
1123 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1128 return error(
"expected ',' before the next machine operand");
1132 MCSymbol *PreInstrSymbol =
nullptr;
1134 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1136 MCSymbol *PostInstrSymbol =
nullptr;
1138 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1140 MDNode *HeapAllocMarker =
nullptr;
1142 if (parseHeapAllocMarker(HeapAllocMarker))
1144 MDNode *PCSections =
nullptr;
1146 if (parsePCSections(PCSections))
1151 unsigned CFIType = 0;
1155 return error(
"expected an integer literal after 'cfi-type'");
1173 unsigned InstrNum = 0;
1177 return error(
"expected an integer literal after 'debug-instr-number'");
1194 if (parseDILocation(Node))
1197 return error(
"expected a metadata node after 'debug-location'");
1200 return error(
"referenced metadata is not a DILocation");
1208 while (!Token.isNewlineOrEOF()) {
1210 if (parseMachineMemoryOperand(
MemOp))
1213 if (Token.isNewlineOrEOF())
1218 return error(
"expected ',' before the next machine memory operand");
1223 const auto &
MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1224 if (!
MCID.isVariadic()) {
1226 if (verifyImplicitOperands(Operands,
MCID))
1230 MI = MF.CreateMachineInstr(
MCID, DebugLocation,
true);
1231 MI->setFlags(Flags);
1235 for (
const auto &Operand : Operands)
1236 MI->addOperand(MF, Operand.Operand);
1238 if (assignRegisterTies(*
MI, Operands))
1241 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1242 if (PostInstrSymbol)
1243 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1244 if (HeapAllocMarker)
1245 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1247 MI->setPCSections(MF, PCSections);
1249 MI->setMMRAMetadata(MF, MMRA);
1251 MI->setCFIType(MF, CFIType);
1253 MI->setDeactivationSymbol(MF, DS);
1254 if (!MemOperands.
empty())
1255 MI->setMemRefs(MF, MemOperands);
1257 MI->setDebugInstrNum(InstrNum);
1264 return error(
"expected a machine basic block reference");
1270 "expected end of string after the machine basic block reference");
1274bool MIParser::parseStandaloneNamedRegister(
Register &
Reg) {
1277 return error(
"expected a named register");
1278 if (parseNamedRegister(
Reg))
1282 return error(
"expected end of string after the register reference");
1286bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
1289 return error(
"expected a virtual register");
1290 if (parseVirtualRegister(Info))
1294 return error(
"expected end of string after the register reference");
1298bool MIParser::parseStandaloneRegister(
Register &
Reg) {
1302 return error(
"expected either a named or virtual register");
1305 if (parseRegister(
Reg, Info))
1310 return error(
"expected end of string after the register reference");
1314bool MIParser::parseStandaloneStackObject(
int &FI) {
1317 return error(
"expected a stack object");
1318 if (parseStackFrameIndex(FI))
1321 return error(
"expected end of string after the stack object reference");
1325bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
1331 if (parseDIExpression(Node))
1334 if (parseDILocation(Node))
1337 return error(
"expected a metadata node");
1340 return error(
"expected end of string after the metadata node");
1344bool MIParser::parseMachineMetadata() {
1347 return error(
"expected a metadata node");
1351 return error(
"expected metadata id after '!'");
1362 return error(
"expected a metadata node");
1366 if (parseMDTuple(MD, IsDistinct))
1369 auto FI = PFS.MachineForwardRefMDNodes.find(
ID);
1370 if (FI != PFS.MachineForwardRefMDNodes.end()) {
1371 FI->second.first->replaceAllUsesWith(MD);
1372 PFS.MachineForwardRefMDNodes.erase(FI);
1374 assert(PFS.MachineMetadataNodes[
ID] == MD &&
"Tracking VH didn't work");
1376 auto [It,
Inserted] = PFS.MachineMetadataNodes.try_emplace(
ID);
1378 return error(
"Metadata id is already used");
1379 It->second.reset(MD);
1385bool MIParser::parseMDTuple(
MDNode *&MD,
bool IsDistinct) {
1387 if (parseMDNodeVector(Elts))
1396 return error(
"expected '{' here");
1417 return error(
"expected end of metadata node");
1425bool MIParser::parseMetadata(
Metadata *&MD) {
1427 return error(
"expected '!' here");
1432 if (parseStringConstant(Str))
1439 return error(
"expected metadata id after '!'");
1441 SMLoc Loc = mapSMLoc(Token.location());
1448 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
1449 if (NodeInfo != PFS.IRSlots.MetadataNodes.end()) {
1450 MD = NodeInfo->second.get();
1454 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
1455 if (NodeInfo != PFS.MachineMetadataNodes.end()) {
1456 MD = NodeInfo->second.get();
1460 auto &FwdRef = PFS.MachineForwardRefMDNodes[
ID];
1461 FwdRef = std::make_pair(
1463 PFS.MachineMetadataNodes[
ID].reset(FwdRef.first.get());
1464 MD = FwdRef.first.get();
1471 return MO.
isDef() ?
"implicit-def" :
"implicit";
1476 assert(
Reg.isPhysical() &&
"expected phys reg");
1483 for (
const auto &
I : Operands) {
1504 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1505 assert(
TRI &&
"Expected target register info");
1506 for (
const auto &
I : ImplicitOperands) {
1509 return error(Operands.
empty() ? Token.location() : Operands.
back().End,
1510 Twine(
"missing implicit register operand '") +
1517bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1586 return error(
"expected a machine instruction");
1587 StringRef InstrName = Token.stringValue();
1588 if (PFS.Target.parseInstrName(InstrName, OpCode))
1589 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1597 if (PFS.Target.getRegisterByName(Name,
Reg))
1598 return error(
Twine(
"unknown register name '") + Name +
"'");
1602bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1607 Info = &PFS.getVRegInfoNamed(Name);
1611bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1613 return parseNamedVirtualRegister(Info);
1618 Info = &PFS.getVRegInfo(
ID);
1623 switch (Token.kind()) {
1628 return parseNamedRegister(
Reg);
1631 if (parseVirtualRegister(Info))
1641bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1643 return error(
"expected '_', register class, or register bank name");
1652 switch (RegInfo.
Kind) {
1658 return error(
Loc,
Twine(
"conflicting register classes, previously: ") +
1667 return error(
Loc,
"register class specification on generic register");
1675 RegBank = PFS.Target.getRegBank(Name);
1677 return error(
Loc,
"expected '_', register class, or register bank name");
1682 switch (RegInfo.
Kind) {
1688 return error(
Loc,
"conflicting generic register banks");
1694 return error(
Loc,
"register bank specification on normal register");
1699bool MIParser::parseRegisterFlag(
RegState &Flags) {
1701 switch (Token.kind()) {
1735 if (OldFlags == Flags)
1738 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1743bool MIParser::parseSubRegisterIndex(
unsigned &SubReg) {
1747 return error(
"expected a subregister index after '.'");
1748 auto Name = Token.stringValue();
1749 SubReg = PFS.Target.getSubRegIndex(Name);
1751 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
1756bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1760 return error(
"expected an integer literal after 'tied-def'");
1770 for (
unsigned I = 0,
E = Operands.
size();
I !=
E; ++
I) {
1771 if (!Operands[
I].TiedDefIdx)
1775 unsigned DefIdx = *Operands[
I].TiedDefIdx;
1777 return error(Operands[
I].Begin,
1778 Twine(
"use of invalid tied-def operand index '" +
1779 Twine(DefIdx) +
"'; instruction has only ") +
1781 const auto &DefOperand = Operands[DefIdx].Operand;
1782 if (!DefOperand.isReg() || !DefOperand.isDef())
1784 return error(Operands[
I].Begin,
1785 Twine(
"use of invalid tied-def operand index '") +
1786 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1787 " isn't a defined register");
1789 for (
const auto &TiedPair : TiedRegisterPairs) {
1790 if (TiedPair.first == DefIdx)
1791 return error(Operands[
I].Begin,
1792 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1793 " is already tied with another register operand");
1795 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1799 for (
const auto &TiedPair : TiedRegisterPairs)
1800 MI.tieOperands(TiedPair.first, TiedPair.second);
1805 std::optional<unsigned> &TiedDefIdx,
1808 while (Token.isRegisterFlag()) {
1809 if (parseRegisterFlag(Flags))
1814 if (!Token.isRegister())
1815 return error(
"expected a register after register flags");
1818 if (parseRegister(
Reg, RegInfo))
1821 unsigned SubReg = 0;
1823 if (parseSubRegisterIndex(SubReg))
1826 return error(
"subregister index expects a virtual register");
1830 return error(
"register class specification expects a virtual register");
1832 if (parseRegisterClassOrBank(*RegInfo))
1841 return error(
"tied-def not supported for defs");
1843 if (parseRegisterTiedDefIndex(Idx))
1848 return error(
"unexpected type on physical register");
1852 if (parseLowLevelType(Token.location(), Ty))
1854 :
error(
"expected tied-def or low-level type after '('");
1861 return error(
"inconsistent type for generic virtual register");
1871 return error(
"generic virtual registers must have a type");
1876 return error(
"cannot have a killed def operand");
1879 return error(
"cannot have a dead use operand");
1896 const APSInt &
Int = Token.integerValue();
1897 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1899 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1902 return error(
"integer literal is too large to be an immediate operand");
1907bool MIParser::parseSymbolicInlineAsmOperand(
unsigned OpIdx,
1911 "expected symbolic inline asm operand");
1915 unsigned ExtraInfo = 0;
1920 StringRef FlagName = Token.stringValue();
1928 .
Case(
"attdialect", 0)
1932 return error(
"unknown inline asm extra info flag '" + FlagName +
"'");
1943 StringRef KindStr = Token.stringValue();
1954 if (K == InvalidKind)
1955 return error(
"unknown inline asm operand kind '" + KindStr +
"'");
1966 return error(
"expected ':' after 'tiedto'");
1969 return error(
"expected '$N' operand number after 'tiedto:'");
1971 if (Token.stringValue().getAsInteger(10, OperandNo))
1972 return error(
"invalid operand number in tiedto constraint");
1975 F.setMatchingOp(OperandNo);
1990 return error(
"expected register class or memory constraint name after ':'");
1992 StringRef ConstraintStr = Token.stringValue();
2026 return error(
"unknown memory constraint '" + ConstraintStr +
"'");
2027 F.setMemConstraint(CC);
2031 PFS.Target.getRegClass(ConstraintStr.
lower());
2033 return error(
"unknown register class '" + ConstraintStr +
"'");
2034 F.setRegClass(RC->
getID());
2043bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
2044 const unsigned OpIdx,
2048 auto Loc = Token.location();
2054 Len += Token.range().size();
2063 Src =
StringRef(
Loc, Len + Token.stringValue().size());
2068 ->
bool { return error(Loc, Msg); }))
2080 auto Source = StringValue.
str();
2085 return ErrCB(
Loc + Err.getColumnNo(), Err.getMessage());
2091 return ::parseIRConstant(
2092 Loc, StringValue, PFS,
C,
2125 "expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
2128 bool Scalar = Token.range().starts_with(
"s");
2129 if (Scalar || Token.range().starts_with(
"i")) {
2138 return error(
"invalid size for scalar type");
2145 if (Token.range().starts_with(
"p")) {
2149 return error(
"invalid address space number");
2156 if (Token.range().starts_with(
"f") || Token.range().starts_with(
"bf")) {
2159 return error(
"invalid size for scalar type");
2161 if (Token.range().starts_with(
"bf") && ScalarSize != 16)
2162 return error(
"invalid size for bfloat");
2165 :
LLT::floatIEEE(ScalarSize);
2172 return error(
Loc,
"expected tN, pA, <M x tN>, <M x pA>, <vscale x M x tN>, "
2173 "or <vscale x M x pA> for GlobalISel type, "
2174 "where t = {'s', 'i', 'f', 'bf'}");
2183 "expected <vscale x M x tN>, where t = {'s', 'i', 'f', 'bf', 'p'}");
2187 auto GetError = [
this, &HasVScale,
Loc]() {
2189 return error(
Loc,
"expected <vscale x M x tN> for vector type, where t = "
2190 "{'s', 'i', 'f', 'bf', 'p'}");
2191 return error(
Loc,
"expected <M x tN> for vector type, where t = {'s', 'i', "
2197 uint64_t NumElements = Token.integerValue().getZExtValue();
2199 return error(
"invalid number of vector elements");
2207 StringRef VectorTyDigits = Token.range();
2216 "expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
2218 Scalar = Token.range().starts_with(
"s");
2219 if (Scalar || Token.range().starts_with(
"i")) {
2222 return error(
"invalid size for scalar element in vector");
2224 }
else if (Token.range().starts_with(
"p")) {
2228 return error(
"invalid address space number");
2231 }
else if (Token.range().starts_with(
"f")) {
2234 return error(
"invalid size for float element in vector");
2236 }
else if (Token.range().starts_with(
"bf")) {
2239 return error(
"invalid size for bfloat element in vector");
2261 return error(
"a typed immediate operand should start with one of 'i', "
2262 "'s', 'f', 'bf', or 'p'");
2265 "expected integers after 'i'/'s'/'f'/'bf'/'p' type identifier");
2267 auto Loc = Token.location();
2271 !(Token.range() ==
"true" || Token.range() ==
"false"))
2272 return error(
"expected an integer literal");
2282 auto Loc = Token.location();
2286 return error(
"expected a floating point literal");
2297 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2299 if (!isxdigit(S[2]))
2302 APInt A(V.size()*4, V, 16);
2306 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2317 return ErrCB(Token.
location(),
"expected unsigned integer");
2320 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2328 if (
A.getBitWidth() > 32)
2329 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2330 Result =
A.getZExtValue();
2336bool MIParser::getUnsigned(
unsigned &Result) {
2337 return ::getUnsigned(
2349 auto MBBInfo = PFS.MBBSlots.find(
Number);
2350 if (MBBInfo == PFS.MBBSlots.end())
2351 return error(
Twine(
"use of undefined machine basic block #") +
2353 MBB = MBBInfo->second;
2356 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2358 " isn't '" + Token.stringValue() +
"'");
2371bool MIParser::parseStackFrameIndex(
int &FI) {
2376 auto ObjectInfo = PFS.StackObjectSlots.find(
ID);
2377 if (ObjectInfo == PFS.StackObjectSlots.end())
2381 if (
const auto *Alloca =
2382 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2383 Name = Alloca->getName();
2384 if (!Token.stringValue().empty() && Token.stringValue() != Name)
2386 "' isn't '" + Token.stringValue() +
"'");
2388 FI = ObjectInfo->second;
2394 if (parseStackFrameIndex(FI))
2400bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2405 auto ObjectInfo = PFS.FixedStackObjectSlots.find(
ID);
2406 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2407 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2410 FI = ObjectInfo->second;
2414bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2416 if (parseFixedStackFrameIndex(FI))
2425 switch (Token.
kind()) {
2430 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2431 Token.
range() +
"'");
2440 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2441 Twine(GVIdx) +
"'");
2450bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2451 return ::parseGlobalValue(
2464 if (parseOperandsOffset(Dest))
2469bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2476 return error(
"use of undefined constant '%const." +
Twine(
ID) +
"'");
2479 if (parseOperandsOffset(Dest))
2489 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(
ID);
2490 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2491 return error(
"use of undefined jump table '%jump-table." +
Twine(
ID) +
"'");
2499 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2502 if (parseOperandsOffset(Dest))
2512 if (parseOperandsOffset(Dest))
2517bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2520 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2521 if (SubRegIndex == 0)
2522 return error(
Twine(
"unknown subregister index '") + Name +
"'");
2528bool MIParser::parseMDNode(
MDNode *&Node) {
2531 auto Loc = Token.location();
2534 return error(
"expected metadata id after '!'");
2538 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
2539 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2540 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
2541 if (NodeInfo == PFS.MachineMetadataNodes.end())
2545 Node = NodeInfo->second.get();
2549bool MIParser::parseDIExpression(
MDNode *&Expr) {
2552 CurrentSource,
Read,
Error, *PFS.MF.getFunction().getParent(),
2554 CurrentSource = CurrentSource.substr(
Read);
2561bool MIParser::parseDILocation(
MDNode *&
Loc) {
2565 bool HaveLine =
false;
2567 unsigned Column = 0;
2569 MDNode *InlinedAt =
nullptr;
2570 bool ImplicitCode =
false;
2571 uint64_t AtomGroup = 0;
2572 uint64_t AtomRank = 0;
2580 if (Token.stringValue() ==
"line") {
2585 Token.integerValue().isSigned())
2586 return error(
"expected unsigned integer");
2587 Line = Token.integerValue().getZExtValue();
2592 if (Token.stringValue() ==
"column") {
2597 Token.integerValue().isSigned())
2598 return error(
"expected unsigned integer");
2599 Column = Token.integerValue().getZExtValue();
2603 if (Token.stringValue() ==
"scope") {
2608 return error(
"expected metadata node");
2610 return error(
"expected DIScope node");
2613 if (Token.stringValue() ==
"inlinedAt") {
2621 if (parseDILocation(InlinedAt))
2624 return error(
"expected metadata node");
2627 return error(
"expected DILocation node");
2630 if (Token.stringValue() ==
"isImplicitCode") {
2635 return error(
"expected true/false");
2639 if (Token.stringValue() ==
"true")
2640 ImplicitCode =
true;
2641 else if (Token.stringValue() ==
"false")
2642 ImplicitCode =
false;
2644 return error(
"expected true/false");
2648 if (Token.stringValue() ==
"atomGroup") {
2653 Token.integerValue().isSigned())
2654 return error(
"expected unsigned integer");
2655 AtomGroup = Token.integerValue().getZExtValue();
2659 if (Token.stringValue() ==
"atomRank") {
2664 Token.integerValue().isSigned())
2665 return error(
"expected unsigned integer");
2666 AtomRank = Token.integerValue().getZExtValue();
2671 return error(
Twine(
"invalid DILocation argument '") +
2672 Token.stringValue() +
"'");
2680 return error(
"DILocation requires line number");
2682 return error(
"DILocation requires a scope");
2685 InlinedAt, ImplicitCode, AtomGroup, AtomRank);
2695 if (parseDIExpression(Node))
2702bool MIParser::parseCFIOffset(
int &
Offset) {
2704 return error(
"expected a cfi offset");
2705 if (Token.integerValue().getSignificantBits() > 32)
2706 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2707 Offset = (int)Token.integerValue().getExtValue();
2712bool MIParser::parseCFIUnsigned(
unsigned &
Value) {
2719bool MIParser::parseCFIRegister(
unsigned &
Reg) {
2721 return error(
"expected a cfi register");
2723 if (parseNamedRegister(LLVMReg))
2725 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2726 assert(
TRI &&
"Expected target register info");
2727 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2729 return error(
"invalid DWARF register");
2730 Reg = (unsigned)DwarfReg;
2735bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2737 return error(
"expected a cfi address space literal");
2738 if (Token.integerValue().isSigned())
2739 return error(
"expected an unsigned integer (cfi address space)");
2745bool MIParser::parseCFIEscapeValues(std::string &Values) {
2748 return error(
"expected a hexadecimal literal");
2752 if (
Value > UINT8_MAX)
2753 return error(
"expected a 8-bit integer (too large)");
2754 Values.push_back(
static_cast<uint8_t
>(
Value));
2761 auto Kind = Token.kind();
2769 if (parseCFIRegister(
Reg))
2784 CFIIndex = MF.addFrameInst(
2788 if (parseCFIRegister(
Reg))
2794 if (parseCFIOffset(
Offset))
2800 if (parseCFIOffset(
Offset))
2802 CFIIndex = MF.addFrameInst(
2824 if (parseCFIRegister(
Reg))
2832 if (parseCFIRegister(
Reg))
2839 parseCFIRegister(Reg2))
2857 unsigned Reg, R1,
R2;
2858 unsigned R1Size, R2Size;
2863 parseCFIUnsigned(R2Size))
2867 nullptr,
Reg, R1, R1Size,
R2, R2Size));
2871 std::vector<MCCFIInstruction::VectorRegisterWithLane> VectorRegisters;
2876 unsigned Lane,
Size;
2879 parseCFIUnsigned(
Size))
2881 VectorRegisters.push_back({VR, Lane,
Size});
2885 nullptr,
Reg, std::move(VectorRegisters)));
2889 unsigned Reg, MaskReg;
2890 unsigned RegSize, MaskRegSize;
2896 parseCFIUnsigned(MaskRegSize) || expectAndConsume(
MIToken::comma) ||
2905 unsigned Reg, SpillReg, MaskReg;
2906 unsigned SpillRegLaneSize, MaskRegSize;
2909 parseCFIRegister(SpillReg) || expectAndConsume(
MIToken::comma) ||
2910 parseCFIUnsigned(SpillRegLaneSize) ||
2912 expectAndConsume(
MIToken::comma) || parseCFIUnsigned(MaskRegSize))
2916 nullptr,
Reg, SpillReg, SpillRegLaneSize, MaskReg, MaskRegSize));
2921 if (parseCFIEscapeValues(Values))
2935 switch (Token.kind()) {
2938 F.getValueSymbolTable()->lookup(Token.stringValue()));
2940 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2944 unsigned SlotNumber = 0;
2947 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2949 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2950 Twine(SlotNumber) +
"'");
2966 return error(
"expected a global value");
2972 return error(
"expected an IR function reference");
2978 return error(
"expected an IR block reference");
2979 if (parseIRBlock(BB, *
F))
2985 if (parseOperandsOffset(Dest))
2994 return error(
"expected syntax intrinsic(@llvm.whatever)");
2997 return error(
"expected syntax intrinsic(@llvm.whatever)");
2999 std::string
Name = std::string(Token.stringValue());
3003 return error(
"expected ')' to terminate intrinsic name");
3008 return error(
"unknown intrinsic name");
3020 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
3023 return error(
"whatever");
3046 return error(
"invalid floating-point predicate");
3061 return error(
"invalid integer predicate");
3067 return error(
"predicate should be terminated by ')'.");
3077 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
3084 const APSInt &
Int = Token.integerValue();
3087 return error(
"expected integer constant");
3094 return error(
"shufflemask should be terminated by ')'.");
3096 if (ShufMask.
size() < 2)
3097 return error(
"shufflemask should have > 1 element");
3109 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3112 return error(
"expected unsigned integer for instruction index");
3113 uint64_t InstrIdx = Token.integerValue().getZExtValue();
3114 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
3115 "Instruction reference's instruction index is too large");
3119 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3122 return error(
"expected unsigned integer for operand index");
3123 uint64_t
OpIdx = Token.integerValue().getZExtValue();
3124 assert(
OpIdx <= std::numeric_limits<unsigned>::max() &&
3125 "Instruction reference's operand index is too large");
3129 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
3141 return error(
"expected the name of the target index");
3143 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
3144 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
3149 if (parseOperandsOffset(Dest))
3154bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
3155 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
3160 uint32_t *
Mask = MF.allocateRegMask();
3164 return error(
"expected a named register");
3166 if (parseNamedRegister(
Reg))
3190 return error(
"expected a valid lane mask value");
3192 "Use correct get-function for lane mask.");
3206bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
3208 uint32_t *
Mask = MF.allocateRegMask();
3214 return error(
"expected a named register");
3216 if (parseNamedRegister(
Reg))
3231bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
3233 std::optional<unsigned> &TiedDefIdx) {
3234 switch (Token.kind()) {
3249 return parseRegisterOperand(Dest, TiedDefIdx);
3253 return parseImmediateOperand(Dest);
3261 return parseFPImmediateOperand(Dest);
3263 return parseMBBOperand(Dest);
3265 return parseStackObjectOperand(Dest);
3267 return parseFixedStackObjectOperand(Dest);
3270 return parseGlobalAddressOperand(Dest);
3272 return parseConstantPoolIndexOperand(Dest);
3274 return parseJumpTableIndexOperand(Dest);
3276 return parseExternalSymbolOperand(Dest);
3278 return parseMCSymbolOperand(Dest);
3280 return parseSubRegisterIndexOperand(Dest);
3283 return parseMetadataOperand(Dest);
3305 return parseCFIOperand(Dest);
3307 return parseBlockAddressOperand(Dest);
3309 return parseIntrinsicOperand(Dest);
3311 return parseTargetIndexOperand(Dest);
3313 return parseLaneMaskOperand(Dest);
3315 return parseLiveoutRegisterMaskOperand(Dest);
3318 return parsePredicateOperand(Dest);
3320 return parseShuffleMaskOperand(Dest);
3322 return parseDbgInstrRefOperand(Dest);
3326 bool IsInlineAsm =
OpCode == TargetOpcode::INLINEASM ||
3327 OpCode == TargetOpcode::INLINEASM_BR;
3329 return parseSymbolicInlineAsmOperand(
OpIdx, Dest);
3332 if (
const auto *RegMask = PFS.Target.getRegMask(Id)) {
3336 }
else if (Id ==
"CustomRegMask") {
3337 return parseCustomRegisterMaskOperand(Dest);
3339 return parseTypedImmediateOperand(Dest);
3343 const auto *
TII = MF.getSubtarget().getInstrInfo();
3344 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3345 return parseTargetImmMnemonic(OpCode,
OpIdx, Dest, *Formatter);
3351 return error(
"expected a machine operand");
3356bool MIParser::parseMachineOperandAndTargetFlags(
3358 std::optional<unsigned> &TiedDefIdx) {
3360 bool HasTargetFlags =
false;
3362 HasTargetFlags =
true;
3367 return error(
"expected the name of the target flag");
3368 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
3369 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
3370 return error(
"use of undefined target flag '" + Token.stringValue() +
3377 return error(
"expected the name of the target flag");
3378 unsigned BitFlag = 0;
3379 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
3380 return error(
"use of undefined target flag '" + Token.stringValue() +
3389 auto Loc = Token.location();
3390 if (parseMachineOperand(OpCode,
OpIdx, Dest, TiedDefIdx))
3392 if (!HasTargetFlags)
3395 return error(
Loc,
"register operands can't have target flags");
3400bool MIParser::parseOffset(int64_t &
Offset) {
3407 return error(
"expected an integer literal after '" + Sign +
"'");
3408 if (Token.integerValue().getSignificantBits() > 64)
3409 return error(
"expected 64-bit integer (too large)");
3410 Offset = Token.integerValue().getExtValue();
3417bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3421 return error(
"expected basic block after 'ir_block_address_taken'");
3423 if (parseIRBlock(BB, MF.getFunction()))
3430bool MIParser::parseAlignment(uint64_t &Alignment) {
3434 return error(
"expected an integer literal after 'align'");
3435 if (getUint64(Alignment))
3440 return error(
"expected a power-of-2 literal after 'align'");
3445bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3449 return error(
"expected an integer literal after 'addrspace'");
3466 switch (Token.
kind()) {
3472 unsigned SlotNumber = 0;
3500 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3504bool MIParser::parseIRValue(
const Value *&V) {
3505 return ::parseIRValue(
3511bool MIParser::getUint64(uint64_t &Result) {
3512 if (Token.hasIntegerValue()) {
3513 if (Token.integerValue().getActiveBits() > 64)
3514 return error(
"expected 64-bit integer (too large)");
3515 Result = Token.integerValue().getZExtValue();
3522 if (
A.getBitWidth() > 64)
3523 return error(
"expected 64-bit integer (too large)");
3530bool MIParser::getHexUint(
APInt &Result) {
3531 return ::getHexUint(Token, Result);
3535 const auto OldFlags =
Flags;
3536 switch (Token.kind()) {
3551 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3552 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3560 if (OldFlags == Flags)
3563 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3569 switch (Token.kind()) {
3571 PSV = MF.getPSVManager().getStack();
3574 PSV = MF.getPSVManager().getGOT();
3577 PSV = MF.getPSVManager().getJumpTable();
3580 PSV = MF.getPSVManager().getConstantPool();
3584 if (parseFixedStackFrameIndex(FI))
3586 PSV = MF.getPSVManager().getFixedStack(FI);
3592 if (parseStackFrameIndex(FI))
3594 PSV = MF.getPSVManager().getFixedStack(FI);
3600 switch (Token.kind()) {
3606 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3610 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3611 MF.createExternalSymbolName(Token.stringValue()));
3615 "expected a global value or an external symbol after 'call-entry'");
3620 const auto *
TII = MF.getSubtarget().getInstrInfo();
3621 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3622 if (Formatter->parseCustomPseudoSourceValue(
3623 Token.stringValue(), MF, PFS, PSV,
3625 return error(Loc, Msg);
3629 return error(
"unable to parse target custom pseudo source value");
3646 if (parseMemoryPseudoSourceValue(PSV))
3659 return error(
"expected an IR value reference");
3660 const Value *
V =
nullptr;
3663 if (V && !
V->getType()->isPointerTy())
3664 return error(
"expected a pointer IR value");
3679 return error(
"expected '(' in syncscope");
3682 if (parseStringConstant(SSN))
3685 SSID =
Context.getOrInsertSyncScopeID(SSN);
3687 return error(
"expected ')' in syncscope");
3693bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3712 return error(
"expected an atomic scope, ordering or a size specification");
3719 while (Token.isMemoryOperandFlag()) {
3720 if (parseMemoryOperandFlag(Flags))
3724 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3725 return error(
"expected 'load' or 'store' memory operation");
3726 if (Token.stringValue() ==
"load")
3740 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3745 if (parseOptionalAtomicOrdering(Order))
3748 if (parseOptionalAtomicOrdering(FailureOrder))
3754 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3755 "memory operation");
3760 if (getUint64(
Size))
3771 if (parseLowLevelType(Token.location(), MemoryType))
3784 if (Token.stringValue() != Word)
3785 return error(
Twine(
"expected '") + Word +
"'");
3788 if (parseMachinePointerInfo(Ptr))
3791 uint64_t BaseAlignment =
3798 switch (Token.kind()) {
3804 if (Ptr.
Offset & (Alignment - 1)) {
3809 return error(
"specified alignment is more aligned than offset");
3811 BaseAlignment = Alignment;
3850 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3851 "'!noalias' or '!range' or '!noalias.addrspace'");
3856 Dest = MF.getMachineMemOperand(Ptr, Flags, MemoryType,
Align(BaseAlignment),
3857 AAInfo,
Range, SSID, Order, FailureOrder);
3861bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3864 "Invalid token for a pre- post-instruction symbol!");
3867 return error(
"expected a symbol after 'pre-instr-symbol'");
3868 Symbol = getOrCreateMCSymbol(Token.stringValue());
3874 return error(
"expected ',' before the next machine operand");
3879bool MIParser::parseHeapAllocMarker(
MDNode *&Node) {
3881 "Invalid token for a heap alloc marker!");
3886 return error(
"expected a MDNode after 'heap-alloc-marker'");
3891 return error(
"expected ',' before the next machine operand");
3896bool MIParser::parsePCSections(
MDNode *&Node) {
3898 "Invalid token for a PC sections!");
3903 return error(
"expected a MDNode after 'pcsections'");
3908 return error(
"expected ',' before the next machine operand");
3913bool MIParser::parseMMRA(
MDNode *&Node) {
3922 return error(
"expected ',' before the next machine operand");
3932 for (
const auto &BB :
F) {
3938 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3945 return Slots2BasicBlocks.
lookup(Slot);
3948const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3949 if (Slots2BasicBlocks.empty())
3955 if (&
F == &MF.getFunction())
3956 return getIRBlock(Slot);
3968 return MF.getContext().getOrCreateSymbol(Name);
3971bool MIParser::parseStringConstant(std::string &Result) {
3973 return error(
"expected string constant");
3974 Result = std::string(Token.stringValue());
3982 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3987 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3993 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3999 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
4005 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
4011 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(Info);
4016 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
4022 return MIParser(PFS,
Error, Src).parsePrefetchTarget(
Target);
4026 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(
Node);
4031 return MIParser(PFS,
Error, Src, SrcRange).parseMachineMetadata();
4039 ErrorCallback(
Loc, Msg);
4043 return ::parseIRValue(Token, PFS, V, ErrorCallback);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the StringMap class.
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static Error parseAlignment(StringRef Str, Align &Alignment, StringRef Name, bool AllowZero=false)
Attempts to parse an alignment component of a specification.
This file defines the DenseMap class.
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
static llvm::Error parse(GsymDataExtractor &Data, uint64_t BaseAddr, LineEntryCallback const &Callback)
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static bool verifyVectorElementCount(uint64_t NumElts)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
MachineInstr unsigned OpIdx
static constexpr unsigned SM(unsigned Version)
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash, uint32_t &Attributes)
Parse Input that contains metadata.
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
bool isNegative() const
Determine sign of this APSInt.
Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & back() const
Get the last element.
size_t size() const
Get the array size.
bool empty() const
Check if the array is empty.
LLVM Basic Block Representation.
static LLVM_ABI BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
static bool isFPPredicate(Predicate P)
static bool isIntPredicate(Predicate P)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
Return the entry for the specified key, or a default constructed value if no such entry exists.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Lightweight error class with error context and mandatory checking.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT token()
Get a low-level token; just a scalar with zero bits (or no size).
static constexpr LLT bfloat16()
static LLT floatIEEE(unsigned SizeInBits)
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createLLVMVectorOffset(MCSymbol *L, unsigned Register, unsigned RegisterSizeInBits, unsigned MaskRegister, unsigned MaskRegisterSizeInBits, int64_t Offset, SMLoc Loc={})
.cfi_llvm_vector_offset Previous value of Register is saved at Offset from CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createLLVMVectorRegisters(MCSymbol *L, unsigned Register, ArrayRef< VectorRegisterWithLane > VectorRegisters, SMLoc Loc={})
.cfi_llvm_vector_registers Previous value of Register is saved in lanes of vector registers.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int64_t Offset, unsigned AddressSpace, SMLoc Loc)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createLLVMVectorRegisterMask(MCSymbol *L, unsigned Register, unsigned SpillRegister, unsigned SpillRegisterLaneSizeInBits, unsigned MaskRegister, unsigned MaskRegisterSizeInBits, SMLoc Loc={})
.cfi_llvm_vector_register_mask Previous value of Register is saved in SpillRegister,...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc={})
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction createLLVMRegisterPair(MCSymbol *L, unsigned Register, unsigned R1, unsigned R1SizeInBits, unsigned R2, unsigned R2SizeInBits, SMLoc Loc={})
.cfi_llvm_register_pair Previous value of Register is saved in R1:R2.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc={})
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc={})
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
Describe properties that are true of each instruction in the target description file.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static LLVM_ABI MDString * get(LLVMContext &Context, StringRef Str)
static MDTuple * getDistinct(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a distinct node.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static TempMDTuple getTemporary(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a temporary node.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void setAlignment(Align A)
Set alignment of the basic block.
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
LLVM_ABI StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
static MachineOperand CreateLaneMask(LaneBitmask LaneMask)
LLVM_ABI bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void noteNewVirtualRegister(Register Reg)
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getNumRegBanks() const
Get the total number of register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
Represents a range in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
std::string str() const
Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
constexpr bool empty() const
Check if the string is empty.
LLVM_ABI std::string lower() const
bool consume_front(char Prefix)
Returns true if this StringRef has the given prefix and removes that prefix.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM_ABI std::string str() const
Return the twine contents as a std::string.
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ BasicBlock
Various leaf nodes.
LLVM_ABI ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ System
Synchronized with respect to all concurrently executing threads.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
RegState
Flags to represent properties of register accesses.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ Define
Register definition.
@ Renamable
Register that may be renamed.
@ Debug
Register 'use' is for debugging purpose.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
bool parsePrefetchTarget(PerFunctionMIParsingState &PFS, CallsiteID &Target, StringRef Src, SMDiagnostic &Error)
LLVM_ABI void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
auto dyn_cast_or_null(const Y &Val)
LLVM_ABI DIExpression * parseDIExpressionBodyAtBeginning(StringRef Asm, unsigned &Read, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots)
constexpr RegState getDefRegState(bool B)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
constexpr bool hasRegState(RegState Value, RegState Test)
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral=false, bool UpperCase=true, bool InsertSeparators=false)
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
LLVM_ABI Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, SMRange SourceRange, SMDiagnostic &Error)
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAliasAddrSpace
The tag specifying the noalias address spaces.
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
LLVM_ABI static const MBBSectionID ExceptionSectionID
LLVM_ABI static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_cfi_llvm_register_pair
@ kw_cfi_llvm_vector_offset
@ kw_inlineasm_br_indirect_target
@ kw_cfi_llvm_vector_registers
@ kw_cfi_llvm_vector_register_mask
@ kw_cfi_aarch64_negate_ra_sign_state_with_pc
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
PerTargetMIParsingState & Target
DenseMap< Register, VRegInfo * > VRegInfos
VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const
bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
void setTarget(const TargetSubtargetInfo &NewSubtarget)
bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
NumberedValues< GlobalValue * > GlobalValues
const RegisterBank * RegBank
union llvm::VRegInfo::@127225073067155374133234315364317264041071000132 D
const TargetRegisterClass * RC
enum llvm::VRegInfo::@374354327266250320012227113300214031244227062232 Kind
bool Explicit
VReg was explicitly specified in the .mir file.