LLVM 23.0.0git
X86InstComments.cpp
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1//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This defines functionality used to emit comments about X86 instructions to
10// an output stream for -fverbose-asm.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstComments.h"
15#include "X86ATTInstPrinter.h"
16#include "X86BaseInfo.h"
17#include "X86MCTargetDesc.h"
18#include "X86ShuffleDecode.h"
19#include "llvm/ADT/Enum.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/Support/raw_ostream.h"
23#include <string_view>
24
25using namespace llvm;
26
27#define CASE_SSE_INS_COMMON(Inst, src) \
28 case X86::Inst##src:
29
30#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
31 case X86::V##Inst##Suffix##src:
32
33#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
34 case X86::V##Inst##Suffix##src##k:
35
36#define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
37 case X86::V##Inst##Suffix##src##kz:
38
39#define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
40 CASE_AVX_INS_COMMON(Inst, Suffix, src) \
41 CASE_MASK_INS_COMMON(Inst, Suffix, src) \
42 CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
43
44#define CASE_MASK_INS_COMMON_INT(Inst, Suffix, src) \
45 case X86::V##Inst##Suffix##src##k_Int:
46
47#define CASE_MASKZ_INS_COMMON_INT(Inst, Suffix, src) \
48 case X86::V##Inst##Suffix##src##kz_Int:
49
50#define CASE_AVX512_INS_COMMON_INT(Inst, Suffix, src) \
51 CASE_AVX_INS_COMMON(Inst, Suffix, src##_Int) \
52 CASE_MASK_INS_COMMON_INT(Inst, Suffix, src) \
53 CASE_MASKZ_INS_COMMON_INT(Inst, Suffix, src)
54
55#define CASE_FPCLASS_PACKED(Inst, src) \
56 CASE_AVX_INS_COMMON(Inst, Z, src##i) \
57 CASE_AVX_INS_COMMON(Inst, Z256, src##i) \
58 CASE_AVX_INS_COMMON(Inst, Z128, src##i) \
59 CASE_MASK_INS_COMMON(Inst, Z, src##i)
60
61#define CASE_FPCLASS_PACKED_MEM(Inst) \
62 CASE_FPCLASS_PACKED(Inst, m) \
63 CASE_FPCLASS_PACKED(Inst, mb)
64
65#define CASE_FPCLASS_SCALAR(Inst, src) \
66 CASE_AVX_INS_COMMON(Inst, Z, src##i) \
67 CASE_MASK_INS_COMMON(Inst, Z, src##i)
68
69#define CASE_PTERNLOG(Inst, src) \
70 CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \
71 CASE_AVX512_INS_COMMON(Inst, Z256, r##src##i) \
72 CASE_AVX512_INS_COMMON(Inst, Z128, r##src##i)
73
74#define CASE_MOVDUP(Inst, src) \
75 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
76 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
77 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
78 CASE_AVX_INS_COMMON(Inst, , r##src) \
79 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
80 CASE_SSE_INS_COMMON(Inst, r##src)
81
82#define CASE_MASK_MOVDUP(Inst, src) \
83 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
84 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
85 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
86
87#define CASE_MASKZ_MOVDUP(Inst, src) \
88 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
89 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
90 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
91
92#define CASE_PMOVZX(Inst, src) \
93 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
94 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
95 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
96 CASE_AVX_INS_COMMON(Inst, , r##src) \
97 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
98 CASE_SSE_INS_COMMON(Inst, r##src)
99
100#define CASE_UNPCK(Inst, src) \
101 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
102 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
103 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
104 CASE_AVX_INS_COMMON(Inst, , r##src) \
105 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
106 CASE_SSE_INS_COMMON(Inst, r##src)
107
108#define CASE_MASK_UNPCK(Inst, src) \
109 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
110 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
111 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
112
113#define CASE_MASKZ_UNPCK(Inst, src) \
114 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
115 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
116 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
117
118#define CASE_SHUF(Inst, suf) \
119 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
120 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
121 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
122 CASE_AVX_INS_COMMON(Inst, , suf) \
123 CASE_AVX_INS_COMMON(Inst, Y, suf) \
124 CASE_SSE_INS_COMMON(Inst, suf)
125
126#define CASE_MASK_SHUF(Inst, src) \
127 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
128 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
129 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
130
131#define CASE_MASKZ_SHUF(Inst, src) \
132 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \
133 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \
134 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
135
136#define CASE_VPERMILPI(Inst, src) \
137 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
138 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
139 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \
140 CASE_AVX_INS_COMMON(Inst, , src##i) \
141 CASE_AVX_INS_COMMON(Inst, Y, src##i)
142
143#define CASE_MASK_VPERMILPI(Inst, src) \
144 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
145 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
146 CASE_MASK_INS_COMMON(Inst, Z128, src##i)
147
148#define CASE_MASKZ_VPERMILPI(Inst, src) \
149 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
150 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
151 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
152
153#define CASE_VPERM(Inst, src) \
154 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
155 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
156 CASE_AVX_INS_COMMON(Inst, Y, src##i)
157
158#define CASE_MASK_VPERM(Inst, src) \
159 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
160 CASE_MASK_INS_COMMON(Inst, Z256, src##i)
161
162#define CASE_MASKZ_VPERM(Inst, src) \
163 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
164 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
165
166#define CASE_VSHUF(Inst, src) \
167 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
168 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
169 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
170 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
171
172#define CASE_MASK_VSHUF(Inst, src) \
173 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
174 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
175 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
176 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
177
178#define CASE_MASKZ_VSHUF(Inst, src) \
179 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
180 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
181 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
182 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
183
184#define CASE_AVX512_FMA(Inst, suf) \
185 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
186 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
187 CASE_AVX512_INS_COMMON(Inst, Z128, suf)
188
189#define CASE_FMA(Inst, suf) \
190 CASE_AVX512_FMA(Inst, suf) \
191 CASE_AVX_INS_COMMON(Inst, , suf) \
192 CASE_AVX_INS_COMMON(Inst, Y, suf)
193
194#define CASE_FMA_PACKED_REG(Inst) \
195 CASE_FMA(Inst##PD, r) \
196 CASE_FMA(Inst##PS, r)
197
198#define CASE_FMA_PACKED_MEM(Inst) \
199 CASE_FMA(Inst##PD, m) \
200 CASE_FMA(Inst##PS, m) \
201 CASE_AVX512_FMA(Inst##PD, mb) \
202 CASE_AVX512_FMA(Inst##PS, mb)
203
204#define CASE_FMA_SCALAR_REG(Inst) \
205 CASE_AVX_INS_COMMON(Inst##SD, , r) \
206 CASE_AVX_INS_COMMON(Inst##SS, , r) \
207 CASE_AVX_INS_COMMON(Inst##SD, , r_Int) \
208 CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \
209 CASE_AVX_INS_COMMON(Inst##SD, Z, r) \
210 CASE_AVX_INS_COMMON(Inst##SS, Z, r) \
211 CASE_AVX512_INS_COMMON_INT(Inst##SD, Z, r) \
212 CASE_AVX512_INS_COMMON_INT(Inst##SS, Z, r)
213
214#define CASE_FMA_SCALAR_MEM(Inst) \
215 CASE_AVX_INS_COMMON(Inst##SD, , m) \
216 CASE_AVX_INS_COMMON(Inst##SS, , m) \
217 CASE_AVX_INS_COMMON(Inst##SD, , m_Int) \
218 CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \
219 CASE_AVX_INS_COMMON(Inst##SD, Z, m) \
220 CASE_AVX_INS_COMMON(Inst##SS, Z, m) \
221 CASE_AVX512_INS_COMMON_INT(Inst##SD, Z, m) \
222 CASE_AVX512_INS_COMMON_INT(Inst##SS, Z, m)
223
224#define CASE_FMA4(Inst, suf) \
225 CASE_AVX_INS_COMMON(Inst, 4, suf) \
226 CASE_AVX_INS_COMMON(Inst, 4Y, suf)
227
228#define CASE_FMA4_PACKED_RR(Inst) \
229 CASE_FMA4(Inst##PD, rr) \
230 CASE_FMA4(Inst##PS, rr)
231
232#define CASE_FMA4_PACKED_RM(Inst) \
233 CASE_FMA4(Inst##PD, rm) \
234 CASE_FMA4(Inst##PS, rm)
235
236#define CASE_FMA4_PACKED_MR(Inst) \
237 CASE_FMA4(Inst##PD, mr) \
238 CASE_FMA4(Inst##PS, mr)
239
240#define CASE_FMA4_SCALAR_RR(Inst) \
241 CASE_AVX_INS_COMMON(Inst##SD4, , rr) \
242 CASE_AVX_INS_COMMON(Inst##SS4, , rr) \
243 CASE_AVX_INS_COMMON(Inst##SD4, , rr_Int) \
244 CASE_AVX_INS_COMMON(Inst##SS4, , rr_Int)
245
246#define CASE_FMA4_SCALAR_RM(Inst) \
247 CASE_AVX_INS_COMMON(Inst##SD4, , rm) \
248 CASE_AVX_INS_COMMON(Inst##SS4, , rm) \
249 CASE_AVX_INS_COMMON(Inst##SD4, , rm_Int) \
250 CASE_AVX_INS_COMMON(Inst##SS4, , rm_Int)
251
252#define CASE_FMA4_SCALAR_MR(Inst) \
253 CASE_AVX_INS_COMMON(Inst##SD4, , mr) \
254 CASE_AVX_INS_COMMON(Inst##SS4, , mr) \
255 CASE_AVX_INS_COMMON(Inst##SD4, , mr_Int) \
256 CASE_AVX_INS_COMMON(Inst##SS4, , mr_Int)
257
258static unsigned getVectorRegSize(MCRegister Reg) {
259 if (X86II::isZMMReg(Reg))
260 return 512;
261 if (X86II::isYMMReg(Reg))
262 return 256;
263 if (X86II::isXMMReg(Reg))
264 return 128;
265 if (Reg >= X86::MM0 && Reg <= X86::MM7)
266 return 64;
267
268 llvm_unreachable("Unknown vector reg!");
269}
270
271static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
272 unsigned OperandIndex) {
273 MCRegister OpReg = MI->getOperand(OperandIndex).getReg();
274 return getVectorRegSize(OpReg) / ScalarSize;
275}
276
277static const char *getRegName(MCRegister Reg) {
278 return X86ATTInstPrinter::getRegisterName(Reg);
279}
280
281/// Wraps the destination register name with AVX512 mask/maskz filtering.
282static void printMasking(raw_ostream &OS, const MCInst *MI,
283 const MCInstrInfo &MCII) {
284 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
285 uint64_t TSFlags = Desc.TSFlags;
286
287 if (!(TSFlags & X86II::EVEX_K))
288 return;
289
290 bool MaskWithZero = (TSFlags & X86II::EVEX_Z);
291 unsigned MaskOp = Desc.getNumDefs();
292
293 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1)
294 ++MaskOp;
295
296 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
297
298 // MASK: zmmX {%kY}
299 OS << " {%" << MaskRegName << "}";
300
301 // MASKZ: zmmX {%kY} {z}
302 if (MaskWithZero)
303 OS << " {z}";
304}
305
306static bool printFMAComments(const MCInst *MI, raw_ostream &OS,
307 const MCInstrInfo &MCII) {
308 const char *Mul1Name = nullptr, *Mul2Name = nullptr, *AccName = nullptr;
309 unsigned NumOperands = MI->getNumOperands();
310 bool RegForm = false;
311 bool Negate = false;
312 StringRef AccStr = "+";
313
314 // The operands for FMA3 instructions without rounding fall into two forms:
315 // dest, src1, src2, src3
316 // dest, src1, mask, src2, src3
317 // Where src3 is either a register or 5 memory address operands. So to find
318 // dest and src1 we can index from the front. To find src2 and src3 we can
319 // index from the end by taking into account memory vs register form when
320 // finding src2.
321
322 // The operands for FMA4 instructions:
323 // dest, src1, src2, src3
324 // Where src2 OR src3 are either a register or 5 memory address operands. So
325 // to find dest and src1 we can index from the front, src2 (reg/mem) follows
326 // and then src3 (reg) will be at the end.
327
328 switch (MI->getOpcode()) {
329 default:
330 return false;
331
332 CASE_FMA4_PACKED_RR(FMADD)
333 CASE_FMA4_SCALAR_RR(FMADD)
334 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
335 [[fallthrough]];
336 CASE_FMA4_PACKED_RM(FMADD)
337 CASE_FMA4_SCALAR_RM(FMADD)
338 Mul2Name = getRegName(MI->getOperand(2).getReg());
339 Mul1Name = getRegName(MI->getOperand(1).getReg());
340 break;
341 CASE_FMA4_PACKED_MR(FMADD)
342 CASE_FMA4_SCALAR_MR(FMADD)
343 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
344 Mul1Name = getRegName(MI->getOperand(1).getReg());
345 break;
346
347 CASE_FMA4_PACKED_RR(FMSUB)
348 CASE_FMA4_SCALAR_RR(FMSUB)
349 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
350 [[fallthrough]];
351 CASE_FMA4_PACKED_RM(FMSUB)
352 CASE_FMA4_SCALAR_RM(FMSUB)
353 Mul2Name = getRegName(MI->getOperand(2).getReg());
354 Mul1Name = getRegName(MI->getOperand(1).getReg());
355 AccStr = "-";
356 break;
357 CASE_FMA4_PACKED_MR(FMSUB)
358 CASE_FMA4_SCALAR_MR(FMSUB)
359 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
360 Mul1Name = getRegName(MI->getOperand(1).getReg());
361 AccStr = "-";
362 break;
363
364 CASE_FMA4_PACKED_RR(FNMADD)
365 CASE_FMA4_SCALAR_RR(FNMADD)
366 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
367 [[fallthrough]];
368 CASE_FMA4_PACKED_RM(FNMADD)
369 CASE_FMA4_SCALAR_RM(FNMADD)
370 Mul2Name = getRegName(MI->getOperand(2).getReg());
371 Mul1Name = getRegName(MI->getOperand(1).getReg());
372 Negate = true;
373 break;
374 CASE_FMA4_PACKED_MR(FNMADD)
375 CASE_FMA4_SCALAR_MR(FNMADD)
376 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
377 Mul1Name = getRegName(MI->getOperand(1).getReg());
378 Negate = true;
379 break;
380
381 CASE_FMA4_PACKED_RR(FNMSUB)
382 CASE_FMA4_SCALAR_RR(FNMSUB)
383 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
384 [[fallthrough]];
385 CASE_FMA4_PACKED_RM(FNMSUB)
386 CASE_FMA4_SCALAR_RM(FNMSUB)
387 Mul2Name = getRegName(MI->getOperand(2).getReg());
388 Mul1Name = getRegName(MI->getOperand(1).getReg());
389 AccStr = "-";
390 Negate = true;
391 break;
392 CASE_FMA4_PACKED_MR(FNMSUB)
393 CASE_FMA4_SCALAR_MR(FNMSUB)
394 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
395 Mul1Name = getRegName(MI->getOperand(1).getReg());
396 AccStr = "-";
397 Negate = true;
398 break;
399
400 CASE_FMA4_PACKED_RR(FMADDSUB)
401 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
402 [[fallthrough]];
403 CASE_FMA4_PACKED_RM(FMADDSUB)
404 Mul2Name = getRegName(MI->getOperand(2).getReg());
405 Mul1Name = getRegName(MI->getOperand(1).getReg());
406 AccStr = "+/-";
407 break;
408 CASE_FMA4_PACKED_MR(FMADDSUB)
409 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
410 Mul1Name = getRegName(MI->getOperand(1).getReg());
411 AccStr = "+/-";
412 break;
413
414 CASE_FMA4_PACKED_RR(FMSUBADD)
415 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
416 [[fallthrough]];
417 CASE_FMA4_PACKED_RM(FMSUBADD)
418 Mul2Name = getRegName(MI->getOperand(2).getReg());
419 Mul1Name = getRegName(MI->getOperand(1).getReg());
420 AccStr = "-/+";
421 break;
422 CASE_FMA4_PACKED_MR(FMSUBADD)
423 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
424 Mul1Name = getRegName(MI->getOperand(1).getReg());
425 AccStr = "-/+";
426 break;
427
428 CASE_FMA_PACKED_REG(FMADD132)
429 CASE_FMA_SCALAR_REG(FMADD132)
430 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
431 RegForm = true;
432 [[fallthrough]];
433 CASE_FMA_PACKED_MEM(FMADD132)
434 CASE_FMA_SCALAR_MEM(FMADD132)
435 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
436 Mul1Name = getRegName(MI->getOperand(1).getReg());
437 break;
438
439 CASE_FMA_PACKED_REG(FMADD213)
440 CASE_FMA_SCALAR_REG(FMADD213)
441 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
442 RegForm = true;
443 [[fallthrough]];
444 CASE_FMA_PACKED_MEM(FMADD213)
445 CASE_FMA_SCALAR_MEM(FMADD213)
446 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
447 Mul2Name = getRegName(MI->getOperand(1).getReg());
448 break;
449
450 CASE_FMA_PACKED_REG(FMADD231)
451 CASE_FMA_SCALAR_REG(FMADD231)
452 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
453 RegForm = true;
454 [[fallthrough]];
455 CASE_FMA_PACKED_MEM(FMADD231)
456 CASE_FMA_SCALAR_MEM(FMADD231)
457 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
458 AccName = getRegName(MI->getOperand(1).getReg());
459 break;
460
461 CASE_FMA_PACKED_REG(FMSUB132)
462 CASE_FMA_SCALAR_REG(FMSUB132)
463 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
464 RegForm = true;
465 [[fallthrough]];
466 CASE_FMA_PACKED_MEM(FMSUB132)
467 CASE_FMA_SCALAR_MEM(FMSUB132)
468 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
469 Mul1Name = getRegName(MI->getOperand(1).getReg());
470 AccStr = "-";
471 break;
472
473 CASE_FMA_PACKED_REG(FMSUB213)
474 CASE_FMA_SCALAR_REG(FMSUB213)
475 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
476 RegForm = true;
477 [[fallthrough]];
478 CASE_FMA_PACKED_MEM(FMSUB213)
479 CASE_FMA_SCALAR_MEM(FMSUB213)
480 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
481 Mul2Name = getRegName(MI->getOperand(1).getReg());
482 AccStr = "-";
483 break;
484
485 CASE_FMA_PACKED_REG(FMSUB231)
486 CASE_FMA_SCALAR_REG(FMSUB231)
487 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
488 RegForm = true;
489 [[fallthrough]];
490 CASE_FMA_PACKED_MEM(FMSUB231)
491 CASE_FMA_SCALAR_MEM(FMSUB231)
492 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
493 AccName = getRegName(MI->getOperand(1).getReg());
494 AccStr = "-";
495 break;
496
497 CASE_FMA_PACKED_REG(FNMADD132)
498 CASE_FMA_SCALAR_REG(FNMADD132)
499 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
500 RegForm = true;
501 [[fallthrough]];
502 CASE_FMA_PACKED_MEM(FNMADD132)
503 CASE_FMA_SCALAR_MEM(FNMADD132)
504 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
505 Mul1Name = getRegName(MI->getOperand(1).getReg());
506 Negate = true;
507 break;
508
509 CASE_FMA_PACKED_REG(FNMADD213)
510 CASE_FMA_SCALAR_REG(FNMADD213)
511 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
512 RegForm = true;
513 [[fallthrough]];
514 CASE_FMA_PACKED_MEM(FNMADD213)
515 CASE_FMA_SCALAR_MEM(FNMADD213)
516 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
517 Mul2Name = getRegName(MI->getOperand(1).getReg());
518 Negate = true;
519 break;
520
521 CASE_FMA_PACKED_REG(FNMADD231)
522 CASE_FMA_SCALAR_REG(FNMADD231)
523 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
524 RegForm = true;
525 [[fallthrough]];
526 CASE_FMA_PACKED_MEM(FNMADD231)
527 CASE_FMA_SCALAR_MEM(FNMADD231)
528 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
529 AccName = getRegName(MI->getOperand(1).getReg());
530 Negate = true;
531 break;
532
533 CASE_FMA_PACKED_REG(FNMSUB132)
534 CASE_FMA_SCALAR_REG(FNMSUB132)
535 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
536 RegForm = true;
537 [[fallthrough]];
538 CASE_FMA_PACKED_MEM(FNMSUB132)
539 CASE_FMA_SCALAR_MEM(FNMSUB132)
540 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
541 Mul1Name = getRegName(MI->getOperand(1).getReg());
542 AccStr = "-";
543 Negate = true;
544 break;
545
546 CASE_FMA_PACKED_REG(FNMSUB213)
547 CASE_FMA_SCALAR_REG(FNMSUB213)
548 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
549 RegForm = true;
550 [[fallthrough]];
551 CASE_FMA_PACKED_MEM(FNMSUB213)
552 CASE_FMA_SCALAR_MEM(FNMSUB213)
553 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
554 Mul2Name = getRegName(MI->getOperand(1).getReg());
555 AccStr = "-";
556 Negate = true;
557 break;
558
559 CASE_FMA_PACKED_REG(FNMSUB231)
560 CASE_FMA_SCALAR_REG(FNMSUB231)
561 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
562 RegForm = true;
563 [[fallthrough]];
564 CASE_FMA_PACKED_MEM(FNMSUB231)
565 CASE_FMA_SCALAR_MEM(FNMSUB231)
566 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
567 AccName = getRegName(MI->getOperand(1).getReg());
568 AccStr = "-";
569 Negate = true;
570 break;
571
572 CASE_FMA_PACKED_REG(FMADDSUB132)
573 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
574 RegForm = true;
575 [[fallthrough]];
576 CASE_FMA_PACKED_MEM(FMADDSUB132)
577 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
578 Mul1Name = getRegName(MI->getOperand(1).getReg());
579 AccStr = "+/-";
580 break;
581
582 CASE_FMA_PACKED_REG(FMADDSUB213)
583 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
584 RegForm = true;
585 [[fallthrough]];
586 CASE_FMA_PACKED_MEM(FMADDSUB213)
587 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
588 Mul2Name = getRegName(MI->getOperand(1).getReg());
589 AccStr = "+/-";
590 break;
591
592 CASE_FMA_PACKED_REG(FMADDSUB231)
593 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
594 RegForm = true;
595 [[fallthrough]];
596 CASE_FMA_PACKED_MEM(FMADDSUB231)
597 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
598 AccName = getRegName(MI->getOperand(1).getReg());
599 AccStr = "+/-";
600 break;
601
602 CASE_FMA_PACKED_REG(FMSUBADD132)
603 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
604 RegForm = true;
605 [[fallthrough]];
606 CASE_FMA_PACKED_MEM(FMSUBADD132)
607 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
608 Mul1Name = getRegName(MI->getOperand(1).getReg());
609 AccStr = "-/+";
610 break;
611
612 CASE_FMA_PACKED_REG(FMSUBADD213)
613 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
614 RegForm = true;
615 [[fallthrough]];
616 CASE_FMA_PACKED_MEM(FMSUBADD213)
617 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
618 Mul2Name = getRegName(MI->getOperand(1).getReg());
619 AccStr = "-/+";
620 break;
621
622 CASE_FMA_PACKED_REG(FMSUBADD231)
623 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
624 RegForm = true;
625 [[fallthrough]];
626 CASE_FMA_PACKED_MEM(FMSUBADD231)
627 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
628 AccName = getRegName(MI->getOperand(1).getReg());
629 AccStr = "-/+";
630 break;
631 }
632
633 const char *DestName = getRegName(MI->getOperand(0).getReg());
634
635 if (!Mul1Name) Mul1Name = "mem";
636 if (!Mul2Name) Mul2Name = "mem";
637 if (!AccName) AccName = "mem";
638
639 OS << DestName;
640 printMasking(OS, MI, MCII);
641 OS << " = ";
642
643 if (Negate)
644 OS << '-';
645
646 OS << '(' << Mul1Name << " * " << Mul2Name << ") " << AccStr << ' '
647 << AccName << '\n';
648
649 return true;
650}
651
652// This table is indexed by the imm8 binary function specified in a
653// vpternlog{d,q} instruction. The symbols {a,b,c} correspond to the three
654// inputs to the binary function. This table was taken from
655// https://gist.github.com/dougallj/81a80cd381988466c4e1c4889ecac95b#file-2-x86-base-txt
656// with slight massaging.
657constexpr EnumStringDef<uint8_t> TernlogFunctionDefs[] = {
658 {{"0"}, 0},
659 {{"~(a | b | c)"}, 1},
660 {{"c & ~(a | b)"}, 2},
661 {{"~(a | b)"}, 3},
662 {{"b & ~(a | c)"}, 4},
663 {{"~(a | c)"}, 5},
664 {{"~a & (b ^ c)"}, 6},
665 {{"~(a | (b & c))"}, 7},
666 {{"b & c & ~a"}, 8},
667 {{"~(a | (b ^ c))"}, 9},
668 {{"c & ~a"}, 10},
669 {{"~a & (c | ~b)"}, 11},
670 {{"b & ~a"}, 12},
671 {{"~a & (b | ~c)"}, 13},
672 {{"~a & (b | c)"}, 14},
673 {{"~a"}, 15},
674 {{"a & ~(b | c)"}, 16},
675 {{"~(b | c)"}, 17},
676 {{"~b & (a ^ c)"}, 18},
677 {{"~((a & c) | b)"}, 19},
678 {{"~c & (a ^ b)"}, 20},
679 {{"~((a & b) | c)"}, 21},
680 {{"a ^ ((a & b) | (b ^ c))"}, 22},
681 {{"(a & (b ^ c)) ^ ~(b & c)"}, 23},
682 {{"(a ^ b) & (a ^ c)"}, 24},
683 {{"~((a & b) | (b ^ c))"}, 25},
684 {{"a ^ ((a & b) | c)"}, 26},
685 {{"(a & c) ^ (c | ~b)"}, 27},
686 {{"a ^ ((a & c) | b)"}, 28},
687 {{"(a & b) ^ (b | ~c)"}, 29},
688 {{"a ^ (b | c)"}, 30},
689 {{"~(a & (b | c))"}, 31},
690 {{"a & c & ~b"}, 32},
691 {{"~(b | (a ^ c))"}, 33},
692 {{"c & ~b"}, 34},
693 {{"~b & (c | ~a)"}, 35},
694 {{"(a ^ b) & (b ^ c)"}, 36},
695 {{"~((a & b) | (a ^ c))"}, 37},
696 {{"b ^ ((a & b) | c)"}, 38},
697 {{"(b & c) ^ (c | ~a)"}, 39},
698 {{"c & (a ^ b)"}, 40},
699 {{"(a | b) ^ ((a & b) | ~c)"}, 41},
700 {{"c & ~(a & b)"}, 42},
701 {{"(c & (a ^ b)) | ~(a | b)"}, 43},
702 {{"(b | c) & (a ^ b)"}, 44},
703 {{"a ^ (b | ~c)"}, 45},
704 {{"(a & b) ^ (b | c)"}, 46},
705 {{"(c & ~b) | ~a"}, 47},
706 {{"a & ~b"}, 48},
707 {{"~b & (a | ~c)"}, 49},
708 {{"~b & (a | c)"}, 50},
709 {{"~b"}, 51},
710 {{"b ^ (a | (b & c))"}, 52},
711 {{"(a & b) ^ (a | ~c)"}, 53},
712 {{"b ^ (a | c)"}, 54},
713 {{"~(b & (a | c))"}, 55},
714 {{"(a | c) & (a ^ b)"}, 56},
715 {{"b ^ (a | ~c)"}, 57},
716 {{"(a & b) ^ (a | c)"}, 58},
717 {{"(c & ~a) | ~b"}, 59},
718 {{"a ^ b"}, 60},
719 {{"~(a | c) | (a ^ b)"}, 61},
720 {{"(c & ~a) | (a ^ b)"}, 62},
721 {{"~(a & b)"}, 63},
722 {{"a & b & ~c"}, 64},
723 {{"~(c | (a ^ b))"}, 65},
724 {{"(a ^ c) & (b ^ c)"}, 66},
725 {{"~((a & c) | (a ^ b))"}, 67},
726 {{"b & ~c"}, 68},
727 {{"~c & (b | ~a)"}, 69},
728 {{"c ^ ((a & c) | b)"}, 70},
729 {{"(b & c) ^ (b | ~a)"}, 71},
730 {{"b & (a ^ c)"}, 72},
731 {{"(a | c) ^ ((a & c) | ~b)"}, 73},
732 {{"(b | c) & (a ^ c)"}, 74},
733 {{"a ^ (c | ~b)"}, 75},
734 {{"b & ~(a & c)"}, 76},
735 {{"(b & (a ^ c)) | ~(a | c)"}, 77},
736 {{"(a & c) ^ (b | c)"}, 78},
737 {{"(b & ~c) | ~a"}, 79},
738 {{"a & ~c"}, 80},
739 {{"~c & (a | ~b)"}, 81},
740 {{"c ^ (a | (b & c))"}, 82},
741 {{"(a & c) ^ (a | ~b)"}, 83},
742 {{"~c & (a | b)"}, 84},
743 {{"~c"}, 85},
744 {{"c ^ (a | b)"}, 86},
745 {{"~(c & (a | b))"}, 87},
746 {{"(a | b) & (a ^ c)"}, 88},
747 {{"c ^ (a | ~b)"}, 89},
748 {{"a ^ c"}, 90},
749 {{"~(a | b) | (a ^ c)"}, 91},
750 {{"(a & c) ^ (a | b)"}, 92},
751 {{"(b & ~a) | ~c"}, 93},
752 {{"(b & ~a) | (a ^ c)"}, 94},
753 {{"~(a & c)"}, 95},
754 {{"a & (b ^ c)"}, 96},
755 {{"~(b ^ c) ^ (a | (b & c))"}, 97},
756 {{"(a | c) & (b ^ c)"}, 98},
757 {{"b ^ (c | ~a)"}, 99},
758 {{"(a | b) & (b ^ c)"}, 100},
759 {{"c ^ (b | ~a)"}, 101},
760 {{"b ^ c"}, 102},
761 {{"~(a | b) | (b ^ c)"}, 103},
762 {{"(a | b) & (c ^ (a & b))"}, 104},
763 {{"b ^ c ^ ~a"}, 105},
764 {{"c ^ (a & b)"}, 106},
765 {{"~(a | b) | (c ^ (a & b))"}, 107},
766 {{"b ^ (a & c)"}, 108},
767 {{"~(a | c) | (b ^ (a & c))"}, 109},
768 {{"(b & ~a) | (b ^ c)"}, 110},
769 {{"~a | (b ^ c)"}, 111},
770 {{"a & ~(b & c)"}, 112},
771 {{"(a & (b ^ c)) | ~(b | c)"}, 113},
772 {{"(b & c) ^ (a | c)"}, 114},
773 {{"(a & ~c) | ~b"}, 115},
774 {{"(b & c) ^ (a | b)"}, 116},
775 {{"(a & ~b) | ~c"}, 117},
776 {{"(a & ~b) | (b ^ c)"}, 118},
777 {{"~(b & c)"}, 119},
778 {{"a ^ (b & c)"}, 120},
779 {{"~(b | c) | (a ^ (b & c))"}, 121},
780 {{"(a & ~b) | (a ^ c)"}, 122},
781 {{"~b | (a ^ c)"}, 123},
782 {{"(a & ~c) | (a ^ b)"}, 124},
783 {{"~c | (a ^ b)"}, 125},
784 {{"(a ^ b) | (a ^ c)"}, 126},
785 {{"~(a & b & c)"}, 127},
786 {{"a & b & c"}, 128},
787 {{"~((a ^ b) | (a ^ c))"}, 129},
788 {{"c & ~(a ^ b)"}, 130},
789 {{"~(a ^ b) & (c | ~a)"}, 131},
790 {{"b & ~(a ^ c)"}, 132},
791 {{"~(a ^ c) & (b | ~a)"}, 133},
792 {{"(b | c) & (a ^ b ^ c)"}, 134},
793 {{"(b & c) ^ ~a"}, 135},
794 {{"b & c"}, 136},
795 {{"~(b ^ c) & (b | ~a)"}, 137},
796 {{"c & (b | ~a)"}, 138},
797 {{"~((b & c) ^ (a | b))"}, 139},
798 {{"b & (c | ~a)"}, 140},
799 {{"~((b & c) ^ (a | c))"}, 141},
800 {{"a ^ ((a ^ b) | (a ^ c))"}, 142},
801 {{"(b & c) | ~a"}, 143},
802 {{"a & ~(b ^ c)"}, 144},
803 {{"~(b ^ c) & (a | ~b)"}, 145},
804 {{"(a | c) & (a ^ b ^ c)"}, 146},
805 {{"(a & c) ^ ~b"}, 147},
806 {{"(a | b) & (a ^ b ^ c)"}, 148},
807 {{"(a & b) ^ ~c"}, 149},
808 {{"a ^ b ^ c"}, 150},
809 {{"~(a | b) | (a ^ b ^ c)"}, 151},
810 {{"~(b ^ c) & (a | b)"}, 152},
811 {{"~(b ^ c)"}, 153},
812 {{"c ^ (a & ~b)"}, 154},
813 {{"~((a | b) & (b ^ c))"}, 155},
814 {{"b ^ (a & ~c)"}, 156},
815 {{"~((a | c) & (b ^ c))"}, 157},
816 {{"(b & c) | (a ^ (b | c))"}, 158},
817 {{"~(a & (b ^ c))"}, 159},
818 {{"a & c"}, 160},
819 {{"~(a ^ c) & (a | ~b)"}, 161},
820 {{"c & (a | ~b)"}, 162},
821 {{"~((a & c) ^ (a | b))"}, 163},
822 {{"~(a ^ c) & (a | b)"}, 164},
823 {{"~(a ^ c)"}, 165},
824 {{"c ^ (b & ~a)"}, 166},
825 {{"~((a | b) & (a ^ c))"}, 167},
826 {{"c & (a | b)"}, 168},
827 {{"~c ^ (a | b)"}, 169},
828 {{"c"}, 170},
829 {{"c | ~(a | b)"}, 171},
830 {{"b ^ (a & (b ^ c))"}, 172},
831 {{"(b & c) | ~(a ^ c)"}, 173},
832 {{"(b & ~a) | c"}, 174},
833 {{"c | ~a"}, 175},
834 {{"a & (c | ~b)"}, 176},
835 {{"~((a & c) ^ (b | c))"}, 177},
836 {{"a ^ ((a ^ c) & (b ^ c))"}, 178},
837 {{"(a & c) | ~b"}, 179},
838 {{"a ^ (b & ~c)"}, 180},
839 {{"~((b | c) & (a ^ c))"}, 181},
840 {{"(a & c) | (a ^ b ^ c)"}, 182},
841 {{"~(b & (a ^ c))"}, 183},
842 {{"a ^ (b & (a ^ c))"}, 184},
843 {{"(a & c) | ~(b ^ c)"}, 185},
844 {{"(a & ~b) | c"}, 186},
845 {{"c | ~b"}, 187},
846 {{"(a & c) | (a ^ b)"}, 188},
847 {{"~((a ^ c) & (b ^ c))"}, 189},
848 {{"c | (a ^ b)"}, 190},
849 {{"c | ~(a & b)"}, 191},
850 {{"a & b"}, 192},
851 {{"~(a ^ b) & (a | ~c)"}, 193},
852 {{"~(a ^ b) & (a | c)"}, 194},
853 {{"~(a ^ b)"}, 195},
854 {{"b & (a | ~c)"}, 196},
855 {{"~((a & b) ^ (a | c))"}, 197},
856 {{"b ^ (c & ~a)"}, 198},
857 {{"~((a | c) & (a ^ b))"}, 199},
858 {{"b & (a | c)"}, 200},
859 {{"~b ^ (a | c)"}, 201},
860 {{"c ^ (a & (b ^ c))"}, 202},
861 {{"(b & c) | ~(a ^ b)"}, 203},
862 {{"b"}, 204},
863 {{"b | ~(a | c)"}, 205},
864 {{"(c & ~a) | b"}, 206},
865 {{"b | ~a"}, 207},
866 {{"a & (b | ~c)"}, 208},
867 {{"~((a & b) ^ (b | c))"}, 209},
868 {{"a ^ (c & ~b)"}, 210},
869 {{"~((b | c) & (a ^ b))"}, 211},
870 {{"a ^ ((a ^ b) & (b ^ c))"}, 212},
871 {{"(a & b) | ~c"}, 213},
872 {{"(a & b) | (a ^ b ^ c)"}, 214},
873 {{"~(c & (a ^ b))"}, 215},
874 {{"a ^ (c & (a ^ b))"}, 216},
875 {{"(a & b) | ~(b ^ c)"}, 217},
876 {{"(a & b) | (a ^ c)"}, 218},
877 {{"~((a ^ b) & (b ^ c))"}, 219},
878 {{"(a & ~c) | b"}, 220},
879 {{"b | ~c"}, 221},
880 {{"b | (a ^ c)"}, 222},
881 {{"b | ~(a & c)"}, 223},
882 {{"a & (b | c)"}, 224},
883 {{"~a ^ (b | c)"}, 225},
884 {{"c ^ (b & (a ^ c))"}, 226},
885 {{"(a & c) | ~(a ^ b)"}, 227},
886 {{"b ^ (c & (a ^ b))"}, 228},
887 {{"(a & b) | ~(a ^ c)"}, 229},
888 {{"(a & b) | (b ^ c)"}, 230},
889 {{"~((a ^ b) & (a ^ c))"}, 231},
890 {{"(a | b) & ((a & b) | c)"}, 232},
891 {{"(a & b) | (b ^ c ^ ~a)"}, 233},
892 {{"(a & b) | c"}, 234},
893 {{"c | ~(a ^ b)"}, 235},
894 {{"(a & c) | b"}, 236},
895 {{"b | ~(a ^ c)"}, 237},
896 {{"b | c"}, 238},
897 {{"~a | b | c"}, 239},
898 {{"a"}, 240},
899 {{"a | ~(b | c)"}, 241},
900 {{"a | (c & ~b)"}, 242},
901 {{"a | ~b"}, 243},
902 {{"a | (b & ~c)"}, 244},
903 {{"a | ~c"}, 245},
904 {{"a | (b ^ c)"}, 246},
905 {{"a | ~(b & c)"}, 247},
906 {{"a | (b & c)"}, 248},
907 {{"a | ~(b ^ c)"}, 249},
908 {{"a | c"}, 250},
909 {{"~b | a | c"}, 251},
910 {{"a | b"}, 252},
911 {{"~c | a | b"}, 253},
912 {{"a | b | c"}, 254},
913 {{"-1"}, 255},
914};
915constexpr auto TernlogFunctions = BUILD_ENUM_STRINGS(TernlogFunctionDefs);
916
917static bool printPTERNLOGComments(const MCInst *MI, raw_ostream &OS,
918 const MCInstrInfo &MCII) {
919 unsigned NumOperands = MI->getNumOperands();
920
921 int Src2Idx;
922 int Src3Idx;
923 switch (MI->getOpcode()) {
924 // dest, src1, src2, src3, tbl
925 // dest, src1, mask, src2, src3, tbl
926 CASE_PTERNLOG(PTERNLOGD, r)
927 CASE_PTERNLOG(PTERNLOGQ, r)
928 Src2Idx = NumOperands - 3;
929 Src3Idx = NumOperands - 2;
930 break;
931
932 // dest, src1, src2, memory, tbl
933 // dest, src1, mask, src2, memory, tbl
934 CASE_PTERNLOG(PTERNLOGD, m)
935 CASE_PTERNLOG(PTERNLOGQ, m)
936 Src2Idx = NumOperands - 7;
937 Src3Idx = -1;
938 break;
939
940 CASE_PTERNLOG(PTERNLOGD, mb)
941 Src2Idx = NumOperands - 7;
942 Src3Idx = -2;
943 break;
944
945 CASE_PTERNLOG(PTERNLOGQ, mb)
946 Src2Idx = NumOperands - 7;
947 Src3Idx = -3;
948 break;
949
950 default:
951 return false;
952 }
953 StringRef DestName = getRegName(MI->getOperand(0).getReg());
954 StringRef Src1Name = getRegName(MI->getOperand(1).getReg());
955 StringRef Src2Name = getRegName(MI->getOperand(Src2Idx).getReg());
956 StringRef Src3Name;
957 switch (Src3Idx) {
958 case -1:
959 Src3Name = "mem";
960 break;
961 case -2:
962 Src3Name = "m32bcst";
963 break;
964 case -3:
965 Src3Name = "m64bcst";
966 break;
967 default:
968 Src3Name = getRegName(MI->getOperand(Src3Idx).getReg());
969 break;
970 }
971 uint8_t TruthTable = MI->getOperand(NumOperands - 1).getImm();
972
973 StringRef SrcNames[] = {Src1Name, Src2Name, Src3Name};
974
975 OS << DestName;
976 printMasking(OS, MI, MCII);
977 OS << " = ";
978
979 static_assert(std::size(TernlogFunctions) == 256);
980 std::string_view BooleanFunction = TernlogFunctions[TruthTable].name();
981
982 while (!BooleanFunction.empty()) {
983 // Print the expression up to the next symbol.
984 size_t SymbolOffset = BooleanFunction.find_first_of("abc");
985 OS << BooleanFunction.substr(0, SymbolOffset);
986 if (SymbolOffset == std::string_view::npos) {
987 // No more symbols, that means we just printed everything.
988 break;
989 }
990 // Let's replace {a,b,c} with Src{1,2,3}Name.
991 char Symbol = BooleanFunction[SymbolOffset];
992 OS << SrcNames[Symbol - 'a'];
993 // Consume the part of the expression we handled.
994 BooleanFunction.remove_prefix(SymbolOffset + 1);
995 }
996 OS << '\n';
997 return true;
998}
999
1000static bool printFPCLASSComments(const MCInst *MI, raw_ostream &OS,
1001 const MCInstrInfo &MCII) {
1002 unsigned NumOperands = MI->getNumOperands();
1003 int SrcIdx;
1004 switch (MI->getOpcode()) {
1005 CASE_FPCLASS_PACKED(FPCLASSBF16, r)
1006 CASE_FPCLASS_PACKED(FPCLASSPH, r)
1007 CASE_FPCLASS_PACKED(FPCLASSPS, r)
1008 CASE_FPCLASS_PACKED(FPCLASSPD, r)
1009 CASE_FPCLASS_SCALAR(FPCLASSSH, r)
1010 CASE_FPCLASS_SCALAR(FPCLASSSS, r)
1011 CASE_FPCLASS_SCALAR(FPCLASSSD, r) {
1012 SrcIdx = NumOperands - 2;
1013 break;
1014 }
1015 CASE_FPCLASS_PACKED_MEM(FPCLASSBF16)
1016 CASE_FPCLASS_PACKED_MEM(FPCLASSPH)
1017 CASE_FPCLASS_PACKED_MEM(FPCLASSPS)
1018 CASE_FPCLASS_PACKED_MEM(FPCLASSPD)
1019 CASE_FPCLASS_SCALAR(FPCLASSSH, m)
1020 CASE_FPCLASS_SCALAR(FPCLASSSS, m)
1021 CASE_FPCLASS_SCALAR(FPCLASSSD, m) {
1022 SrcIdx = -1;
1023 break;
1024 }
1025 default:
1026 return false;
1027 }
1028 StringRef DestName = getRegName(MI->getOperand(0).getReg());
1029 StringRef SrcName =
1030 SrcIdx != -1 ? getRegName(MI->getOperand(SrcIdx).getReg()) : "mem";
1031
1032 OS << DestName;
1033 printMasking(OS, MI, MCII);
1034 OS << " = ";
1035
1036 uint8_t Categories = MI->getOperand(NumOperands - 1).getImm();
1037 if (Categories == 0) {
1038 OS << "false";
1039 } else {
1040 static constexpr StringLiteral CategoryNames[] = {
1041 "QuietNaN",
1042 "PositiveZero",
1043 "NegativeZero",
1044 "PositiveInfinity",
1045 "NegativeInfinity",
1046 "Subnormal",
1047 "Negative",
1048 "SignalingNaN",
1049 };
1050 bool Conjoin = false;
1051 for (size_t I = 0, E = std::size(CategoryNames); I != E; ++I) {
1052 if (Categories & (1 << I)) {
1053 if (Conjoin)
1054 OS << " | ";
1055 Conjoin = true;
1056 OS << "is" << CategoryNames[I] << '(' << SrcName << ')';
1057 }
1058 }
1059 }
1060 OS << '\n';
1061 return true;
1062}
1063
1064//===----------------------------------------------------------------------===//
1065// Top Level Entrypoint
1066//===----------------------------------------------------------------------===//
1067
1068/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
1069/// newline terminated strings to the specified string if desired. This
1070/// information is shown in disassembly dumps when verbose assembly is enabled.
1071bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
1072 const MCInstrInfo &MCII) {
1073 // If this is a shuffle operation, the switch should fill in this state.
1074 SmallVector<int, 8> ShuffleMask;
1075 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
1076 unsigned NumOperands = MI->getNumOperands();
1077 bool RegForm = false;
1078
1079 if (printFMAComments(MI, OS, MCII))
1080 return true;
1081
1082 if (printPTERNLOGComments(MI, OS, MCII))
1083 return true;
1084
1085 if (printFPCLASSComments(MI, OS, MCII))
1086 return true;
1087
1088 switch (MI->getOpcode()) {
1089 default:
1090 // Not an instruction for which we can decode comments.
1091 return false;
1092
1093 case X86::BLENDPDrri:
1094 case X86::VBLENDPDrri:
1095 case X86::VBLENDPDYrri:
1096 Src2Name = getRegName(MI->getOperand(2).getReg());
1097 [[fallthrough]];
1098 case X86::BLENDPDrmi:
1099 case X86::VBLENDPDrmi:
1100 case X86::VBLENDPDYrmi:
1101 if (MI->getOperand(NumOperands - 1).isImm())
1102 DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0),
1103 MI->getOperand(NumOperands - 1).getImm(),
1104 ShuffleMask);
1105 Src1Name = getRegName(MI->getOperand(1).getReg());
1106 DestName = getRegName(MI->getOperand(0).getReg());
1107 break;
1108
1109 case X86::BLENDPSrri:
1110 case X86::VBLENDPSrri:
1111 case X86::VBLENDPSYrri:
1112 Src2Name = getRegName(MI->getOperand(2).getReg());
1113 [[fallthrough]];
1114 case X86::BLENDPSrmi:
1115 case X86::VBLENDPSrmi:
1116 case X86::VBLENDPSYrmi:
1117 if (MI->getOperand(NumOperands - 1).isImm())
1118 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
1119 MI->getOperand(NumOperands - 1).getImm(),
1120 ShuffleMask);
1121 Src1Name = getRegName(MI->getOperand(1).getReg());
1122 DestName = getRegName(MI->getOperand(0).getReg());
1123 break;
1124
1125 case X86::PBLENDWrri:
1126 case X86::VPBLENDWrri:
1127 case X86::VPBLENDWYrri:
1128 Src2Name = getRegName(MI->getOperand(2).getReg());
1129 [[fallthrough]];
1130 case X86::PBLENDWrmi:
1131 case X86::VPBLENDWrmi:
1132 case X86::VPBLENDWYrmi:
1133 if (MI->getOperand(NumOperands - 1).isImm())
1134 DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0),
1135 MI->getOperand(NumOperands - 1).getImm(),
1136 ShuffleMask);
1137 Src1Name = getRegName(MI->getOperand(1).getReg());
1138 DestName = getRegName(MI->getOperand(0).getReg());
1139 break;
1140
1141 case X86::VPBLENDDrri:
1142 case X86::VPBLENDDYrri:
1143 Src2Name = getRegName(MI->getOperand(2).getReg());
1144 [[fallthrough]];
1145 case X86::VPBLENDDrmi:
1146 case X86::VPBLENDDYrmi:
1147 if (MI->getOperand(NumOperands - 1).isImm())
1148 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
1149 MI->getOperand(NumOperands - 1).getImm(),
1150 ShuffleMask);
1151 Src1Name = getRegName(MI->getOperand(1).getReg());
1152 DestName = getRegName(MI->getOperand(0).getReg());
1153 break;
1154
1155 case X86::INSERTPSrri:
1156 case X86::VINSERTPSrri:
1157 case X86::VINSERTPSZrri:
1158 Src2Name = getRegName(MI->getOperand(2).getReg());
1159 DestName = getRegName(MI->getOperand(0).getReg());
1160 Src1Name = getRegName(MI->getOperand(1).getReg());
1161 if (MI->getOperand(NumOperands - 1).isImm())
1162 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask,
1163 /*SrcIsMem=*/false);
1164 break;
1165
1166 case X86::INSERTPSrmi:
1167 case X86::VINSERTPSrmi:
1168 case X86::VINSERTPSZrmi:
1169 DestName = getRegName(MI->getOperand(0).getReg());
1170 Src1Name = getRegName(MI->getOperand(1).getReg());
1171 if (MI->getOperand(NumOperands - 1).isImm())
1172 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask,
1173 /*SrcIsMem=*/true);
1174 break;
1175
1176 case X86::MOVLHPSrr:
1177 case X86::VMOVLHPSrr:
1178 case X86::VMOVLHPSZrr:
1179 Src2Name = getRegName(MI->getOperand(2).getReg());
1180 Src1Name = getRegName(MI->getOperand(1).getReg());
1181 DestName = getRegName(MI->getOperand(0).getReg());
1182 DecodeMOVLHPSMask(2, ShuffleMask);
1183 break;
1184
1185 case X86::MOVHLPSrr:
1186 case X86::VMOVHLPSrr:
1187 case X86::VMOVHLPSZrr:
1188 Src2Name = getRegName(MI->getOperand(2).getReg());
1189 Src1Name = getRegName(MI->getOperand(1).getReg());
1190 DestName = getRegName(MI->getOperand(0).getReg());
1191 DecodeMOVHLPSMask(2, ShuffleMask);
1192 break;
1193
1194 case X86::MOVHPDrm:
1195 case X86::VMOVHPDrm:
1196 case X86::VMOVHPDZ128rm:
1197 Src1Name = getRegName(MI->getOperand(1).getReg());
1198 DestName = getRegName(MI->getOperand(0).getReg());
1199 DecodeInsertElementMask(2, 1, 1, ShuffleMask);
1200 break;
1201
1202 case X86::MOVHPSrm:
1203 case X86::VMOVHPSrm:
1204 case X86::VMOVHPSZ128rm:
1205 Src1Name = getRegName(MI->getOperand(1).getReg());
1206 DestName = getRegName(MI->getOperand(0).getReg());
1207 DecodeInsertElementMask(4, 2, 2, ShuffleMask);
1208 break;
1209
1210 case X86::MOVLPDrm:
1211 case X86::VMOVLPDrm:
1212 case X86::VMOVLPDZ128rm:
1213 Src1Name = getRegName(MI->getOperand(1).getReg());
1214 DestName = getRegName(MI->getOperand(0).getReg());
1215 DecodeInsertElementMask(2, 0, 1, ShuffleMask);
1216 break;
1217
1218 case X86::MOVLPSrm:
1219 case X86::VMOVLPSrm:
1220 case X86::VMOVLPSZ128rm:
1221 Src1Name = getRegName(MI->getOperand(1).getReg());
1222 DestName = getRegName(MI->getOperand(0).getReg());
1223 DecodeInsertElementMask(4, 0, 2, ShuffleMask);
1224 break;
1225
1226 CASE_MOVDUP(MOVSLDUP, r)
1227 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1228 [[fallthrough]];
1229
1230 CASE_MOVDUP(MOVSLDUP, m)
1231 DestName = getRegName(MI->getOperand(0).getReg());
1232 DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
1233 break;
1234
1235 CASE_MOVDUP(MOVSHDUP, r)
1236 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1237 [[fallthrough]];
1238
1239 CASE_MOVDUP(MOVSHDUP, m)
1240 DestName = getRegName(MI->getOperand(0).getReg());
1241 DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
1242 break;
1243
1244 CASE_MOVDUP(MOVDDUP, r)
1245 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1246 [[fallthrough]];
1247
1248 CASE_MOVDUP(MOVDDUP, m)
1249 DestName = getRegName(MI->getOperand(0).getReg());
1250 DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask);
1251 break;
1252
1253 case X86::PSLLDQri:
1254 case X86::VPSLLDQri:
1255 case X86::VPSLLDQYri:
1256 case X86::VPSLLDQZ128ri:
1257 case X86::VPSLLDQZ256ri:
1258 case X86::VPSLLDQZri:
1259 Src1Name = getRegName(MI->getOperand(1).getReg());
1260 [[fallthrough]];
1261 case X86::VPSLLDQZ128mi:
1262 case X86::VPSLLDQZ256mi:
1263 case X86::VPSLLDQZmi:
1264 DestName = getRegName(MI->getOperand(0).getReg());
1265 if (MI->getOperand(NumOperands - 1).isImm())
1266 DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0),
1267 MI->getOperand(NumOperands - 1).getImm(),
1268 ShuffleMask);
1269 break;
1270
1271 case X86::PSRLDQri:
1272 case X86::VPSRLDQri:
1273 case X86::VPSRLDQYri:
1274 case X86::VPSRLDQZ128ri:
1275 case X86::VPSRLDQZ256ri:
1276 case X86::VPSRLDQZri:
1277 Src1Name = getRegName(MI->getOperand(1).getReg());
1278 [[fallthrough]];
1279 case X86::VPSRLDQZ128mi:
1280 case X86::VPSRLDQZ256mi:
1281 case X86::VPSRLDQZmi:
1282 DestName = getRegName(MI->getOperand(0).getReg());
1283 if (MI->getOperand(NumOperands - 1).isImm())
1284 DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0),
1285 MI->getOperand(NumOperands - 1).getImm(),
1286 ShuffleMask);
1287 break;
1288
1289 CASE_SHUF(PALIGNR, rri)
1290 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1291 RegForm = true;
1292 [[fallthrough]];
1293
1294 CASE_SHUF(PALIGNR, rmi)
1295 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1296 DestName = getRegName(MI->getOperand(0).getReg());
1297 if (MI->getOperand(NumOperands - 1).isImm())
1298 DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0),
1299 MI->getOperand(NumOperands - 1).getImm(),
1300 ShuffleMask);
1301 break;
1302
1303 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
1304 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
1305 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
1306 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1307 RegForm = true;
1308 [[fallthrough]];
1309
1310 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
1311 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
1312 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
1313 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1314 DestName = getRegName(MI->getOperand(0).getReg());
1315 if (MI->getOperand(NumOperands - 1).isImm())
1316 DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0),
1317 MI->getOperand(NumOperands - 1).getImm(),
1318 ShuffleMask);
1319 break;
1320
1321 CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
1322 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
1323 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
1324 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1325 RegForm = true;
1326 [[fallthrough]];
1327
1328 CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
1329 CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
1330 CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
1331 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1332 DestName = getRegName(MI->getOperand(0).getReg());
1333 if (MI->getOperand(NumOperands - 1).isImm())
1334 DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0),
1335 MI->getOperand(NumOperands - 1).getImm(),
1336 ShuffleMask);
1337 break;
1338
1339 CASE_SHUF(PSHUFD, ri)
1340 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1341 [[fallthrough]];
1342
1343 CASE_SHUF(PSHUFD, mi)
1344 DestName = getRegName(MI->getOperand(0).getReg());
1345 if (MI->getOperand(NumOperands - 1).isImm())
1346 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
1347 MI->getOperand(NumOperands - 1).getImm(),
1348 ShuffleMask);
1349 break;
1350
1351 CASE_SHUF(PSHUFHW, ri)
1352 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1353 [[fallthrough]];
1354
1355 CASE_SHUF(PSHUFHW, mi)
1356 DestName = getRegName(MI->getOperand(0).getReg());
1357 if (MI->getOperand(NumOperands - 1).isImm())
1358 DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0),
1359 MI->getOperand(NumOperands - 1).getImm(),
1360 ShuffleMask);
1361 break;
1362
1363 CASE_SHUF(PSHUFLW, ri)
1364 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1365 [[fallthrough]];
1366
1367 CASE_SHUF(PSHUFLW, mi)
1368 DestName = getRegName(MI->getOperand(0).getReg());
1369 if (MI->getOperand(NumOperands - 1).isImm())
1370 DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0),
1371 MI->getOperand(NumOperands - 1).getImm(),
1372 ShuffleMask);
1373 break;
1374
1375 case X86::MMX_PSHUFWri:
1376 Src1Name = getRegName(MI->getOperand(1).getReg());
1377 [[fallthrough]];
1378
1379 case X86::MMX_PSHUFWmi:
1380 DestName = getRegName(MI->getOperand(0).getReg());
1381 if (MI->getOperand(NumOperands - 1).isImm())
1382 DecodePSHUFMask(4, 16, MI->getOperand(NumOperands - 1).getImm(),
1383 ShuffleMask);
1384 break;
1385
1386 case X86::PSWAPDrr:
1387 Src1Name = getRegName(MI->getOperand(1).getReg());
1388 [[fallthrough]];
1389
1390 case X86::PSWAPDrm:
1391 DestName = getRegName(MI->getOperand(0).getReg());
1392 DecodePSWAPMask(2, ShuffleMask);
1393 break;
1394
1395 CASE_UNPCK(PUNPCKHBW, r)
1396 case X86::MMX_PUNPCKHBWrr:
1397 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1398 RegForm = true;
1399 [[fallthrough]];
1400
1401 CASE_UNPCK(PUNPCKHBW, m)
1402 case X86::MMX_PUNPCKHBWrm:
1403 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1404 DestName = getRegName(MI->getOperand(0).getReg());
1405 DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
1406 break;
1407
1408 CASE_UNPCK(PUNPCKHWD, r)
1409 case X86::MMX_PUNPCKHWDrr:
1410 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1411 RegForm = true;
1412 [[fallthrough]];
1413
1414 CASE_UNPCK(PUNPCKHWD, m)
1415 case X86::MMX_PUNPCKHWDrm:
1416 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1417 DestName = getRegName(MI->getOperand(0).getReg());
1418 DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
1419 break;
1420
1421 CASE_UNPCK(PUNPCKHDQ, r)
1422 case X86::MMX_PUNPCKHDQrr:
1423 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1424 RegForm = true;
1425 [[fallthrough]];
1426
1427 CASE_UNPCK(PUNPCKHDQ, m)
1428 case X86::MMX_PUNPCKHDQrm:
1429 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1430 DestName = getRegName(MI->getOperand(0).getReg());
1431 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1432 break;
1433
1434 CASE_UNPCK(PUNPCKHQDQ, r)
1435 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1436 RegForm = true;
1437 [[fallthrough]];
1438
1439 CASE_UNPCK(PUNPCKHQDQ, m)
1440 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1441 DestName = getRegName(MI->getOperand(0).getReg());
1442 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1443 break;
1444
1445 CASE_UNPCK(PUNPCKLBW, r)
1446 case X86::MMX_PUNPCKLBWrr:
1447 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1448 RegForm = true;
1449 [[fallthrough]];
1450
1451 CASE_UNPCK(PUNPCKLBW, m)
1452 case X86::MMX_PUNPCKLBWrm:
1453 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1454 DestName = getRegName(MI->getOperand(0).getReg());
1455 DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
1456 break;
1457
1458 CASE_UNPCK(PUNPCKLWD, r)
1459 case X86::MMX_PUNPCKLWDrr:
1460 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1461 RegForm = true;
1462 [[fallthrough]];
1463
1464 CASE_UNPCK(PUNPCKLWD, m)
1465 case X86::MMX_PUNPCKLWDrm:
1466 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1467 DestName = getRegName(MI->getOperand(0).getReg());
1468 DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
1469 break;
1470
1471 CASE_UNPCK(PUNPCKLDQ, r)
1472 case X86::MMX_PUNPCKLDQrr:
1473 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1474 RegForm = true;
1475 [[fallthrough]];
1476
1477 CASE_UNPCK(PUNPCKLDQ, m)
1478 case X86::MMX_PUNPCKLDQrm:
1479 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1480 DestName = getRegName(MI->getOperand(0).getReg());
1481 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1482 break;
1483
1484 CASE_UNPCK(PUNPCKLQDQ, r)
1485 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1486 RegForm = true;
1487 [[fallthrough]];
1488
1489 CASE_UNPCK(PUNPCKLQDQ, m)
1490 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1491 DestName = getRegName(MI->getOperand(0).getReg());
1492 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1493 break;
1494
1495 CASE_SHUF(SHUFPD, rri)
1496 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1497 RegForm = true;
1498 [[fallthrough]];
1499
1500 CASE_SHUF(SHUFPD, rmi)
1501 if (MI->getOperand(NumOperands - 1).isImm())
1502 DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64,
1503 MI->getOperand(NumOperands - 1).getImm(), ShuffleMask);
1504 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1505 DestName = getRegName(MI->getOperand(0).getReg());
1506 break;
1507
1508 CASE_SHUF(SHUFPS, rri)
1509 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1510 RegForm = true;
1511 [[fallthrough]];
1512
1513 CASE_SHUF(SHUFPS, rmi)
1514 if (MI->getOperand(NumOperands - 1).isImm())
1515 DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32,
1516 MI->getOperand(NumOperands - 1).getImm(),
1517 ShuffleMask);
1518 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1519 DestName = getRegName(MI->getOperand(0).getReg());
1520 break;
1521
1522 CASE_VSHUF(64X2, r)
1523 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1524 RegForm = true;
1525 [[fallthrough]];
1526
1527 CASE_VSHUF(64X2, m)
1528 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64,
1529 MI->getOperand(NumOperands - 1).getImm(),
1530 ShuffleMask);
1531 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1532 DestName = getRegName(MI->getOperand(0).getReg());
1533 break;
1534
1535 CASE_VSHUF(32X4, r)
1536 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1537 RegForm = true;
1538 [[fallthrough]];
1539
1540 CASE_VSHUF(32X4, m)
1541 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32,
1542 MI->getOperand(NumOperands - 1).getImm(),
1543 ShuffleMask);
1544 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1545 DestName = getRegName(MI->getOperand(0).getReg());
1546 break;
1547
1548 CASE_UNPCK(UNPCKLPD, r)
1549 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1550 RegForm = true;
1551 [[fallthrough]];
1552
1553 CASE_UNPCK(UNPCKLPD, m)
1554 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1555 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1556 DestName = getRegName(MI->getOperand(0).getReg());
1557 break;
1558
1559 CASE_UNPCK(UNPCKLPS, r)
1560 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1561 RegForm = true;
1562 [[fallthrough]];
1563
1564 CASE_UNPCK(UNPCKLPS, m)
1565 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1566 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1567 DestName = getRegName(MI->getOperand(0).getReg());
1568 break;
1569
1570 CASE_UNPCK(UNPCKHPD, r)
1571 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1572 RegForm = true;
1573 [[fallthrough]];
1574
1575 CASE_UNPCK(UNPCKHPD, m)
1576 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1577 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1578 DestName = getRegName(MI->getOperand(0).getReg());
1579 break;
1580
1581 CASE_UNPCK(UNPCKHPS, r)
1582 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1583 RegForm = true;
1584 [[fallthrough]];
1585
1586 CASE_UNPCK(UNPCKHPS, m)
1587 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1588 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1589 DestName = getRegName(MI->getOperand(0).getReg());
1590 break;
1591
1592 CASE_VPERMILPI(PERMILPS, r)
1593 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1594 [[fallthrough]];
1595
1596 CASE_VPERMILPI(PERMILPS, m)
1597 if (MI->getOperand(NumOperands - 1).isImm())
1598 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
1599 MI->getOperand(NumOperands - 1).getImm(),
1600 ShuffleMask);
1601 DestName = getRegName(MI->getOperand(0).getReg());
1602 break;
1603
1604 CASE_VPERMILPI(PERMILPD, r)
1605 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1606 [[fallthrough]];
1607
1608 CASE_VPERMILPI(PERMILPD, m)
1609 if (MI->getOperand(NumOperands - 1).isImm())
1610 DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64,
1611 MI->getOperand(NumOperands - 1).getImm(),
1612 ShuffleMask);
1613 DestName = getRegName(MI->getOperand(0).getReg());
1614 break;
1615
1616 case X86::VPERM2F128rri:
1617 case X86::VPERM2I128rri:
1618 Src2Name = getRegName(MI->getOperand(2).getReg());
1619 [[fallthrough]];
1620
1621 case X86::VPERM2F128rmi:
1622 case X86::VPERM2I128rmi:
1623 // For instruction comments purpose, assume the 256-bit vector is v4i64.
1624 if (MI->getOperand(NumOperands - 1).isImm())
1625 DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),
1626 ShuffleMask);
1627 Src1Name = getRegName(MI->getOperand(1).getReg());
1628 DestName = getRegName(MI->getOperand(0).getReg());
1629 break;
1630
1631 CASE_VPERM(PERMPD, r)
1632 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1633 [[fallthrough]];
1634
1635 CASE_VPERM(PERMPD, m)
1636 if (MI->getOperand(NumOperands - 1).isImm())
1637 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1638 MI->getOperand(NumOperands - 1).getImm(),
1639 ShuffleMask);
1640 DestName = getRegName(MI->getOperand(0).getReg());
1641 break;
1642
1643 CASE_VPERM(PERMQ, r)
1644 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1645 [[fallthrough]];
1646
1647 CASE_VPERM(PERMQ, m)
1648 if (MI->getOperand(NumOperands - 1).isImm())
1649 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1650 MI->getOperand(NumOperands - 1).getImm(),
1651 ShuffleMask);
1652 DestName = getRegName(MI->getOperand(0).getReg());
1653 break;
1654
1655 case X86::MOVSDrr:
1656 case X86::VMOVSDrr:
1657 case X86::VMOVSDZrr:
1658 Src2Name = getRegName(MI->getOperand(2).getReg());
1659 Src1Name = getRegName(MI->getOperand(1).getReg());
1660 DecodeScalarMoveMask(2, false, ShuffleMask);
1661 DestName = getRegName(MI->getOperand(0).getReg());
1662 break;
1663
1664 case X86::MOVSSrr:
1665 case X86::VMOVSSrr:
1666 case X86::VMOVSSZrr:
1667 Src2Name = getRegName(MI->getOperand(2).getReg());
1668 Src1Name = getRegName(MI->getOperand(1).getReg());
1669 DecodeScalarMoveMask(4, false, ShuffleMask);
1670 DestName = getRegName(MI->getOperand(0).getReg());
1671 break;
1672
1673 case X86::VMOVSHZrr:
1674 Src2Name = getRegName(MI->getOperand(2).getReg());
1675 Src1Name = getRegName(MI->getOperand(1).getReg());
1676 DecodeScalarMoveMask(8, false, ShuffleMask);
1677 DestName = getRegName(MI->getOperand(0).getReg());
1678 break;
1679
1680 case X86::MOVPQI2QIrr:
1681 case X86::MOVZPQILo2PQIrr:
1682 case X86::VMOVPQI2QIrr:
1683 case X86::VMOVPQI2QIZrr:
1684 case X86::VMOVZPQILo2PQIrr:
1685 case X86::VMOVZPQILo2PQIZrr:
1686 Src1Name = getRegName(MI->getOperand(1).getReg());
1687 DecodeZeroMoveLowMask(2, ShuffleMask);
1688 DestName = getRegName(MI->getOperand(0).getReg());
1689 break;
1690
1691 case X86::EXTRQI:
1692 if (MI->getOperand(2).isImm() &&
1693 MI->getOperand(3).isImm())
1694 DecodeEXTRQIMask(16, 8, MI->getOperand(2).getImm(),
1695 MI->getOperand(3).getImm(), ShuffleMask);
1696
1697 DestName = getRegName(MI->getOperand(0).getReg());
1698 Src1Name = getRegName(MI->getOperand(1).getReg());
1699 break;
1700
1701 case X86::INSERTQI:
1702 if (MI->getOperand(3).isImm() &&
1703 MI->getOperand(4).isImm())
1704 DecodeINSERTQIMask(16, 8, MI->getOperand(3).getImm(),
1705 MI->getOperand(4).getImm(), ShuffleMask);
1706
1707 DestName = getRegName(MI->getOperand(0).getReg());
1708 Src1Name = getRegName(MI->getOperand(1).getReg());
1709 Src2Name = getRegName(MI->getOperand(2).getReg());
1710 break;
1711
1712 case X86::VBROADCASTF128rm:
1713 case X86::VBROADCASTI128rm:
1714 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z256, rm)
1715 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z256, rm)
1716 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1717 DestName = getRegName(MI->getOperand(0).getReg());
1718 break;
1719 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z, rm)
1720 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z, rm)
1721 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1722 DestName = getRegName(MI->getOperand(0).getReg());
1723 break;
1724 CASE_AVX512_INS_COMMON(BROADCASTF64X4, Z, rm)
1725 CASE_AVX512_INS_COMMON(BROADCASTI64X4, Z, rm)
1726 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1727 DestName = getRegName(MI->getOperand(0).getReg());
1728 break;
1729 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1730 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1731 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1732 DestName = getRegName(MI->getOperand(0).getReg());
1733 break;
1734 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z, rm)
1735 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z, rm)
1736 DecodeSubVectorBroadcast(16, 4, ShuffleMask);
1737 DestName = getRegName(MI->getOperand(0).getReg());
1738 break;
1739 CASE_AVX512_INS_COMMON(BROADCASTF32X8, Z, rm)
1740 CASE_AVX512_INS_COMMON(BROADCASTI32X8, Z, rm)
1741 DecodeSubVectorBroadcast(16, 8, ShuffleMask);
1742 DestName = getRegName(MI->getOperand(0).getReg());
1743 break;
1744 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, rr)
1745 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1746 [[fallthrough]];
1747 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, rm)
1748 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1749 DestName = getRegName(MI->getOperand(0).getReg());
1750 break;
1751 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, rr)
1752 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, rr)
1753 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1754 [[fallthrough]];
1755 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, rm)
1756 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, rm)
1757 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1758 DestName = getRegName(MI->getOperand(0).getReg());
1759 break;
1760 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, rr)
1761 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, rr)
1762 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1763 [[fallthrough]];
1764 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, rm)
1765 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, rm)
1766 DecodeSubVectorBroadcast(16, 2, ShuffleMask);
1767 DestName = getRegName(MI->getOperand(0).getReg());
1768 break;
1769
1770 CASE_PMOVZX(PMOVZXBW, r)
1771 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1772 DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), false,
1773 ShuffleMask);
1774 DestName = getRegName(MI->getOperand(0).getReg());
1775 break;
1776
1777 CASE_PMOVZX(PMOVZXBD, r)
1778 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1779 DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), false,
1780 ShuffleMask);
1781 DestName = getRegName(MI->getOperand(0).getReg());
1782 break;
1783
1784 CASE_PMOVZX(PMOVZXBQ, r)
1785 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1786 DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), false,
1787 ShuffleMask);
1788 DestName = getRegName(MI->getOperand(0).getReg());
1789 break;
1790
1791 CASE_PMOVZX(PMOVZXWD, r)
1792 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1793 DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), false,
1794 ShuffleMask);
1795 DestName = getRegName(MI->getOperand(0).getReg());
1796 break;
1797
1798 CASE_PMOVZX(PMOVZXWQ, r)
1799 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1800 DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), false,
1801 ShuffleMask);
1802 DestName = getRegName(MI->getOperand(0).getReg());
1803 break;
1804
1805 CASE_PMOVZX(PMOVZXDQ, r)
1806 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1807 DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), false,
1808 ShuffleMask);
1809 DestName = getRegName(MI->getOperand(0).getReg());
1810 break;
1811 }
1812
1813 // The only comments we decode are shuffles, so give up if we were unable to
1814 // decode a shuffle mask.
1815 if (ShuffleMask.empty())
1816 return false;
1817
1818 if (!DestName) DestName = Src1Name;
1819 if (DestName) {
1820 OS << DestName;
1821 printMasking(OS, MI, MCII);
1822 } else
1823 OS << "mem";
1824
1825 OS << " = ";
1826
1827 // If the two sources are the same, canonicalize the input elements to be
1828 // from the first src so that we get larger element spans.
1829 if (Src1Name == Src2Name) {
1830 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1831 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
1832 ShuffleMask[i] >= (int)e) // From second mask.
1833 ShuffleMask[i] -= e;
1834 }
1835 }
1836
1837 // The shuffle mask specifies which elements of the src1/src2 fill in the
1838 // destination, with a few sentinel values. Loop through and print them
1839 // out.
1840 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1841 if (i != 0)
1842 OS << ',';
1843 if (ShuffleMask[i] == SM_SentinelZero) {
1844 OS << "zero";
1845 continue;
1846 }
1847
1848 // Otherwise, it must come from src1 or src2. Print the span of elements
1849 // that comes from this src.
1850 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1851 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1852 OS << (SrcName ? SrcName : "mem") << '[';
1853 bool IsFirst = true;
1854 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1855 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1856 if (!IsFirst)
1857 OS << ',';
1858 else
1859 IsFirst = false;
1860 if (ShuffleMask[i] == SM_SentinelUndef)
1861 OS << "u";
1862 else
1863 OS << ShuffleMask[i] % ShuffleMask.size();
1864 ++i;
1865 }
1866 OS << ']';
1867 --i; // For loop increments element #.
1868 }
1869 OS << '\n';
1870
1871 // We successfully added a comment to this instruction.
1872 return true;
1873}
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
BUILD_ENUM_STRINGS
#define BUILD_ENUM_STRINGS(Tab)
Definition Enum.h:120
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2126
CASE_VPERM
#define CASE_VPERM(Inst, src)
Definition X86InstComments.cpp:153
CASE_FPCLASS_PACKED_MEM
#define CASE_FPCLASS_PACKED_MEM(Inst)
Definition X86InstComments.cpp:61
CASE_FMA_SCALAR_REG
#define CASE_FMA_SCALAR_REG(Inst)
Definition X86InstComments.cpp:204
printPTERNLOGComments
static bool printPTERNLOGComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
Definition X86InstComments.cpp:917
CASE_FPCLASS_PACKED
#define CASE_FPCLASS_PACKED(Inst, src)
Definition X86InstComments.cpp:55
getVectorRegSize
static unsigned getVectorRegSize(MCRegister Reg)
Definition X86InstComments.cpp:258
CASE_VPERMILPI
#define CASE_VPERMILPI(Inst, src)
Definition X86InstComments.cpp:136
CASE_FMA4_SCALAR_MR
#define CASE_FMA4_SCALAR_MR(Inst)
Definition X86InstComments.cpp:252
printFMAComments
static bool printFMAComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
Definition X86InstComments.cpp:306
CASE_SHUF
#define CASE_SHUF(Inst, suf)
Definition X86InstComments.cpp:118
CASE_FMA4_PACKED_RM
#define CASE_FMA4_PACKED_RM(Inst)
Definition X86InstComments.cpp:232
CASE_MOVDUP
#define CASE_MOVDUP(Inst, src)
Definition X86InstComments.cpp:74
CASE_FMA_SCALAR_MEM
#define CASE_FMA_SCALAR_MEM(Inst)
Definition X86InstComments.cpp:214
CASE_FMA4_SCALAR_RR
#define CASE_FMA4_SCALAR_RR(Inst)
Definition X86InstComments.cpp:240
getRegOperandNumElts
static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, unsigned OperandIndex)
Definition X86InstComments.cpp:271
CASE_FMA4_PACKED_MR
#define CASE_FMA4_PACKED_MR(Inst)
Definition X86InstComments.cpp:236
CASE_AVX512_INS_COMMON
#define CASE_AVX512_INS_COMMON(Inst, Suffix, src)
Definition X86InstComments.cpp:39
TernlogFunctionDefs
constexpr EnumStringDef< uint8_t > TernlogFunctionDefs[]
Definition X86InstComments.cpp:657
printFPCLASSComments
static bool printFPCLASSComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
Definition X86InstComments.cpp:1000
getRegName
static const char * getRegName(MCRegister Reg)
Definition X86InstComments.cpp:277
CASE_PMOVZX
#define CASE_PMOVZX(Inst, src)
Definition X86InstComments.cpp:92
CASE_VSHUF
#define CASE_VSHUF(Inst, src)
Definition X86InstComments.cpp:166
CASE_FMA_PACKED_MEM
#define CASE_FMA_PACKED_MEM(Inst)
Definition X86InstComments.cpp:198
printMasking
static void printMasking(raw_ostream &OS, const MCInst *MI, const MCInstrInfo &MCII)
Wraps the destination register name with AVX512 mask/maskz filtering.
Definition X86InstComments.cpp:282
CASE_FPCLASS_SCALAR
#define CASE_FPCLASS_SCALAR(Inst, src)
Definition X86InstComments.cpp:65
CASE_FMA4_SCALAR_RM
#define CASE_FMA4_SCALAR_RM(Inst)
Definition X86InstComments.cpp:246
TernlogFunctions
constexpr auto TernlogFunctions
Definition X86InstComments.cpp:915
CASE_FMA4_PACKED_RR
#define CASE_FMA4_PACKED_RR(Inst)
Definition X86InstComments.cpp:228
CASE_FMA_PACKED_REG
#define CASE_FMA_PACKED_REG(Inst)
Definition X86InstComments.cpp:194
CASE_PTERNLOG
#define CASE_PTERNLOG(Inst, src)
Definition X86InstComments.cpp:69
CASE_UNPCK
#define CASE_UNPCK(Inst, src)
Definition X86InstComments.cpp:100
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:199
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition MCInstrInfo.h:90
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:41
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1236
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition StringRef.h:888
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::X86ATTInstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg)
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint64_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::X86II::isZMMReg
bool isZMMReg(MCRegister Reg)
Definition X86BaseInfo.h:1179
llvm::X86II::isXMMReg
bool isXMMReg(MCRegister Reg)
Definition X86BaseInfo.h:1159
llvm::X86II::isYMMReg
bool isYMMReg(MCRegister Reg)
Definition X86BaseInfo.h:1169
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::DecodeZeroExtendMask
void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl< int > &ShuffleMask)
Decode a zero extension instruction as a shuffle mask.
Definition X86ShuffleDecode.cpp:371
llvm::EmitAnyX86InstComments
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...
Definition X86InstComments.cpp:1071
llvm::DecodeMOVHLPSMask
void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl< int > &ShuffleMask)
Decode a MOVHLPS instruction as a v2f64/v4f32 shuffle mask.
Definition X86ShuffleDecode.cpp:61
llvm::DecodeZeroMoveLowMask
void DecodeZeroMoveLowMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Decode a move lower and zero upper instruction as a shuffle mask.
Definition X86ShuffleDecode.cpp:385
llvm::DecodeInsertElementMask
void DecodeInsertElementMask(unsigned NumElts, unsigned Idx, unsigned Len, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:50
llvm::DecodePSHUFLWMask
void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshuflw.
Definition X86ShuffleDecode.cpp:178
llvm::DecodeBLENDMask
void DecodeBLENDMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a BLEND immediate mask into a shuffle mask.
Definition X86ShuffleDecode.cpp:315
llvm::decodeVSHUF64x2FamilyMask
void decodeVSHUF64x2FamilyMask(unsigned NumElts, unsigned ScalarSize, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a shuffle packed values at 128-bit granularity (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) immed...
Definition X86ShuffleDecode.cpp:264
llvm::DecodeVPERMMask
void DecodeVPERMMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for VPERMQ/VPERMPD.
Definition X86ShuffleDecode.cpp:364
llvm::DecodeEXTRQIMask
void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, SmallVectorImpl< int > &ShuffleMask)
Decode a SSE4A EXTRQ instruction as a shuffle mask.
Definition X86ShuffleDecode.cpp:400
llvm::DecodePSRLDQMask
void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:112
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:26
llvm::DecodeINSERTPSMask
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl< int > &ShuffleMask, bool SrcIsMem)
Decode a 128-bit INSERTPS instruction as a v4f32 shuffle mask.
Definition X86ShuffleDecode.cpp:26
llvm::DecodeVPERM2X128Mask
void DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:281
llvm::DecodeMOVLHPSMask
void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl< int > &ShuffleMask)
Decode a MOVLHPS instruction as a v2f64/v4f32 shuffle mask.
Definition X86ShuffleDecode.cpp:70
llvm::DecodePSWAPMask
void DecodePSWAPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Decodes a PSWAPD 3DNow! instruction.
Definition X86ShuffleDecode.cpp:192
llvm::DecodeINSERTQIMask
void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, SmallVectorImpl< int > &ShuffleMask)
Decode a SSE4A INSERTQ instruction as a shuffle mask.
Definition X86ShuffleDecode.cpp:437
llvm::DecodeVALIGNMask
void DecodeVALIGNMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:139
llvm::DecodeScalarMoveMask
void DecodeScalarMoveMask(unsigned NumElts, bool IsLoad, SmallVectorImpl< int > &ShuffleMask)
Decode a scalar float move instruction as a shuffle mask.
Definition X86ShuffleDecode.cpp:391
llvm::DecodePALIGNRMask
void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:125
llvm::DecodeMOVSLDUPMask
void DecodeMOVSLDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:78
llvm::DecodeSubVectorBroadcast
void DecodeSubVectorBroadcast(unsigned DstNumElts, unsigned SrcNumElts, SmallVectorImpl< int > &ShuffleMask)
Decodes a broadcast of a subvector to a larger vector type.
Definition X86ShuffleDecode.cpp:255
llvm::DecodeUNPCKLMask
void DecodeUNPCKLMask(unsigned NumElts, unsigned ScalarBits, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for unpcklps/unpcklpd and punpckl*.
Definition X86ShuffleDecode.cpp:234
llvm::DecodePSLLDQMask
void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:100
llvm::DecodeUNPCKHMask
void DecodeUNPCKHMask(unsigned NumElts, unsigned ScalarBits, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for unpckhps/unpckhpd and punpckh*.
Definition X86ShuffleDecode.cpp:218
llvm::DecodePSHUFMask
void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshufd/pshufw/vpermilpd/vpermilps.
Definition X86ShuffleDecode.cpp:148
llvm::DecodeMOVDDUPMask
void DecodeMOVDDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:92
llvm::DecodeSHUFPMask
void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for shufp*.
Definition X86ShuffleDecode.cpp:201
llvm::DecodePSHUFHWMask
void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshufhw.
Definition X86ShuffleDecode.cpp:164
llvm::DecodeMOVSHDUPMask
void DecodeMOVSHDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition X86ShuffleDecode.cpp:85
llvm::SM_SentinelUndef
@ SM_SentinelUndef
Definition X86ShuffleDecode.h:28
llvm::SM_SentinelZero
@ SM_SentinelZero
Definition X86ShuffleDecode.h:28
raw_ostream.h
llvm::EnumStringDef
Compile-time data representation of enum entries.
Definition Enum.h:47
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