X86InstrInfo.h File Reference

#include "MCTargetDesc/X86BaseInfo.h"
#include "X86InstrFMA3Info.h"
#include "X86RegisterInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include <vector>
#include "X86GenInstrInfo.inc"

Go to the source code of this file.

Classes
class	llvm::X86InstrInfo

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::X86
	Define some predicates that are used for node matching.

Macros
#define	GET_INSTRINFO_HEADER
#define	GET_INSTRINFO_HELPER_DECLS

Enumerations
enum	llvm::X86MachineCombinerPattern : unsigned { llvm::DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START }
enum	llvm::X86::AsmComments { llvm::X86::AC_EVEX_2_LEGACY = MachineInstr::TAsmComments , llvm::X86::AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1 , llvm::X86::AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1 }

Functions
std::pair< CondCode, bool >	llvm::X86::getX86ConditionCode (CmpInst::Predicate Predicate)
	Return a pair of condition code for the given predicate and whether the instruction operands should be swaped to match the condition code.
unsigned	llvm::X86::getCMovOpcode (unsigned RegBytes, bool HasMemoryOperand=false, bool HasNDD=false)
	Return a cmov opcode for the given register size in bytes, and operand type.
int	llvm::X86::getCondSrcNoFromDesc (const MCInstrDesc &MCID)
	Return the source operand # for condition code by MCID.
CondCode	llvm::X86::getCondFromMI (const MachineInstr &MI)
	Return the condition code of the instruction.
CondCode	llvm::X86::getCondFromBranch (const MachineInstr &MI)
CondCode	llvm::X86::getCondFromSETCC (const MachineInstr &MI)
CondCode	llvm::X86::getCondFromCMov (const MachineInstr &MI)
CondCode	llvm::X86::getCondFromCFCMov (const MachineInstr &MI)
CondCode	llvm::X86::getCondFromCCMP (const MachineInstr &MI)
int	llvm::X86::getCCMPCondFlagsFromCondCode (CondCode CC)
unsigned	llvm::X86::getNFVariant (unsigned Opc)
unsigned	llvm::X86::getNonNDVariant (unsigned Opc)
CondCode	llvm::X86::GetOppositeBranchCondition (CondCode CC)
	GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
unsigned	llvm::X86::getVPCMPImmForCond (ISD::CondCode CC)
	Get the VPCMP immediate for the given condition.
unsigned	llvm::X86::getSwappedVPCMPImm (unsigned Imm)
	Get the VPCMP immediate if the opcodes are swapped.
unsigned	llvm::X86::getSwappedVPCOMImm (unsigned Imm)
	Get the VPCOM immediate if the opcodes are swapped.
unsigned	llvm::X86::getSwappedVCMPImm (unsigned Imm)
	Get the VCMP immediate if the opcodes are swapped.
unsigned	llvm::X86::getVectorRegisterWidth (const MCOperandInfo &Info)
	Get the width of the vector register operand.
bool	llvm::X86::isX87Instruction (MachineInstr &MI)
	Check if the instruction is X87 instruction.
int	llvm::X86::getFirstAddrOperandIdx (const MachineInstr &MI)
	Return the index of the instruction's first address operand, if it has a memory reference, or -1 if it has none.
const Constant *	llvm::X86::getConstantFromPool (const MachineInstr &MI, unsigned OpNo)
	Find any constant pool entry associated with a specific instruction operand.
static bool	llvm::isGlobalStubReference (unsigned char TargetFlag)
	isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for a global, not the global itself.
static bool	llvm::isGlobalRelativeToPICBase (unsigned char TargetFlag)
	isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg).
static bool	llvm::isScale (const MachineOperand &MO)
static bool	llvm::isLeaMem (const MachineInstr &MI, unsigned Op)
static bool	llvm::isMem (const MachineInstr &MI, unsigned Op)
static bool	llvm::isAddMemInstrWithRelocation (const MachineInstr &MI)
static bool	llvm::isMemInstrWithGOTPCREL (const MachineInstr &MI)

Macro Definition Documentation

GET_INSTRINFO_HEADER

#define GET_INSTRINFO_HEADER

Definition at line 23 of file X86InstrInfo.h.

GET_INSTRINFO_HELPER_DECLS

#define GET_INSTRINFO_HELPER_DECLS

Definition at line 656 of file X86InstrInfo.h.