llvm::AArch64Subtarget Member List

This is the complete list of members for llvm::AArch64Subtarget, including all inherited members.

AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool IsStreaming=false, bool IsStreamingCompatible=false, bool HasMinSize=false)	llvm::AArch64Subtarget
addrSinkUsingGEPs() const override	llvm::AArch64Subtarget	inline
adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override	llvm::AArch64Subtarget
ARMProcFamily	llvm::AArch64Subtarget	protected
ARMProcFamilyEnum enum name	llvm::AArch64Subtarget
CacheLineSize	llvm::AArch64Subtarget	protected
CallLoweringInfo	llvm::AArch64Subtarget	protected
classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const	llvm::AArch64Subtarget
classifyGlobalFunctionReference(const GlobalValue *GV) const override	llvm::AArch64Subtarget	inline
ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const	llvm::AArch64Subtarget
CustomCallSavedXRegs	llvm::AArch64Subtarget	protected
DefaultSVETFOpts	llvm::AArch64Subtarget	protected
enableEarlyIfConversion() const override	llvm::AArch64Subtarget
enableMachinePipeliner() const override	llvm::AArch64Subtarget
enableMachineScheduler() const override	llvm::AArch64Subtarget	inline
enablePostRAScheduler() const override	llvm::AArch64Subtarget	inline
EnableSubregLiveness	llvm::AArch64Subtarget	protected
enableSubRegLiveness() const override	llvm::AArch64Subtarget	inline
EpilogueVectorizationMinVF	llvm::AArch64Subtarget	protected
FrameLowering	llvm::AArch64Subtarget	protected
GatherOverhead	llvm::AArch64Subtarget	protected
Generic enum value	llvm::AArch64Subtarget
getAuthenticatedLRCheckMethod(const MachineFunction &MF) const	llvm::AArch64Subtarget
getCacheLineSize() const override	llvm::AArch64Subtarget	inline
getCallLowering() const override	llvm::AArch64Subtarget
getChkStkName() const	llvm::AArch64Subtarget	inline
getCustomPBQPConstraints() const override	llvm::AArch64Subtarget
getEpilogueVectorizationMinVF() const	llvm::AArch64Subtarget	inline
getFrameLowering() const override	llvm::AArch64Subtarget	inline
getGatherOverhead() const	llvm::AArch64Subtarget	inline
getInlineAsmLowering() const override	llvm::AArch64Subtarget
getInstrInfo() const override	llvm::AArch64Subtarget	inline
getInstructionSelector() const override	llvm::AArch64Subtarget
getLegalizerInfo() const override	llvm::AArch64Subtarget
getMaxBytesForLoopAlignment() const	llvm::AArch64Subtarget	inline
getMaximumJumpTableSize() const	llvm::AArch64Subtarget	inline
getMaxInterleaveFactor() const	llvm::AArch64Subtarget	inline
getMaxPrefetchIterationsAhead() const override	llvm::AArch64Subtarget	inline
getMaxSVEVectorSizeInBits() const	llvm::AArch64Subtarget	inline
getMinimumJumpTableEntries() const	llvm::AArch64Subtarget	inline
getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override	llvm::AArch64Subtarget	inline
getMinSVEVectorSizeInBits() const	llvm::AArch64Subtarget	inline
getMinVectorRegisterBitWidth() const	llvm::AArch64Subtarget	inline
getNumXRegisterReserved() const	llvm::AArch64Subtarget	inline
getPrefetchDistance() const override	llvm::AArch64Subtarget	inline
getPrefFunctionAlignment() const	llvm::AArch64Subtarget	inline
getPrefLoopAlignment() const	llvm::AArch64Subtarget	inline
getProcFamily() const	llvm::AArch64Subtarget	inline
getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const	llvm::AArch64Subtarget
getRegBankInfo() const override	llvm::AArch64Subtarget
getRegisterInfo() const override	llvm::AArch64Subtarget	inline
getScatterOverhead() const	llvm::AArch64Subtarget	inline
getSelectionDAGInfo() const override	llvm::AArch64Subtarget	inline
getStreamingHazardSize() const	llvm::AArch64Subtarget	inline
getSVETailFoldingDefaultOpts() const	llvm::AArch64Subtarget	inline
getSVEVectorSizeInBits() const	llvm::AArch64Subtarget	inline
getTargetLowering() const override	llvm::AArch64Subtarget	inline
getTargetTriple() const	llvm::AArch64Subtarget	inline
getVectorInsertExtractBaseCost() const	llvm::AArch64Subtarget
getVScaleForTuning() const	llvm::AArch64Subtarget	inline
hasCustomCallingConv() const	llvm::AArch64Subtarget	inline
hasFusion() const	llvm::AArch64Subtarget	inline
InlineAsmLoweringInfo	llvm::AArch64Subtarget	protected
InstrInfo	llvm::AArch64Subtarget	protected
InstSelector	llvm::AArch64Subtarget	protected
isCallingConvWin64(CallingConv::ID CC, bool IsVarArg) const	llvm::AArch64Subtarget	inline
IsLittle	llvm::AArch64Subtarget	protected
isLittleEndian() const	llvm::AArch64Subtarget	inline
isLRReservedForRA() const	llvm::AArch64Subtarget	inline
isNeonAvailable() const	llvm::AArch64Subtarget	inline
isNonStreamingSVEorSME2Available() const	llvm::AArch64Subtarget	inline
IsStreaming	llvm::AArch64Subtarget	protected
isStreaming() const	llvm::AArch64Subtarget	inline
IsStreamingCompatible	llvm::AArch64Subtarget	protected
isStreamingCompatible() const	llvm::AArch64Subtarget	inline
isStreamingSVEAvailable() const	llvm::AArch64Subtarget	inline
isSVEAvailable() const	llvm::AArch64Subtarget	inline
isSVEorStreamingSVEAvailable() const	llvm::AArch64Subtarget	inline
isTargetAndroid() const	llvm::AArch64Subtarget	inline
isTargetCOFF() const	llvm::AArch64Subtarget	inline
isTargetDarwin() const	llvm::AArch64Subtarget	inline
isTargetELF() const	llvm::AArch64Subtarget	inline
isTargetFuchsia() const	llvm::AArch64Subtarget	inline
isTargetILP32() const	llvm::AArch64Subtarget	inline
isTargetIOS() const	llvm::AArch64Subtarget	inline
isTargetLinux() const	llvm::AArch64Subtarget	inline
isTargetMachO() const	llvm::AArch64Subtarget	inline
isTargetWindows() const	llvm::AArch64Subtarget	inline
isWindowsArm64EC() const	llvm::AArch64Subtarget	inline
isX16X17Safer() const	llvm::AArch64Subtarget
isXRaySupported() const override	llvm::AArch64Subtarget	inline
isXRegCustomCalleeSaved(size_t i) const	llvm::AArch64Subtarget	inline
isXRegisterReserved(size_t i) const	llvm::AArch64Subtarget	inline
isXRegisterReservedForRA(size_t i) const	llvm::AArch64Subtarget	inline
Legalizer	llvm::AArch64Subtarget	protected
MaxBytesForLoopAlignment	llvm::AArch64Subtarget	protected
MaxInterleaveFactor	llvm::AArch64Subtarget	protected
MaxJumpTableSize	llvm::AArch64Subtarget	protected
MaxPrefetchIterationsAhead	llvm::AArch64Subtarget	protected
MaxSVEVectorSizeInBits	llvm::AArch64Subtarget	protected
MinimumJumpTableEntries	llvm::AArch64Subtarget	protected
MinPrefetchStride	llvm::AArch64Subtarget	protected
MinSVEVectorSizeInBits	llvm::AArch64Subtarget	protected
MinVectorRegisterBitWidth	llvm::AArch64Subtarget	protected
mirFileLoaded(MachineFunction &MF) const override	llvm::AArch64Subtarget
overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override	llvm::AArch64Subtarget
ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)	llvm::AArch64Subtarget
PrefetchDistance	llvm::AArch64Subtarget	protected
PrefFunctionAlignment	llvm::AArch64Subtarget	protected
PrefLoopAlignment	llvm::AArch64Subtarget	protected
RegBankInfo	llvm::AArch64Subtarget	protected
ReserveXRegister	llvm::AArch64Subtarget	protected
ReserveXRegisterForRA	llvm::AArch64Subtarget	protected
ScatterOverhead	llvm::AArch64Subtarget	protected
StreamingHazardSize	llvm::AArch64Subtarget	protected
supportsAddressTopByteIgnored() const	llvm::AArch64Subtarget
swiftAsyncContextIsDynamicallySet() const	llvm::AArch64Subtarget	inline
TargetTriple	llvm::AArch64Subtarget	protected
TLInfo	llvm::AArch64Subtarget	protected
TSInfo	llvm::AArch64Subtarget	protected
useAA() const override	llvm::AArch64Subtarget
useDFAforSMS() const override	llvm::AArch64Subtarget	inline
useScalarIncVL() const	llvm::AArch64Subtarget
useSmallAddressing() const	llvm::AArch64Subtarget	inline
useSVEForFixedLengthVectors() const	llvm::AArch64Subtarget	inline
useSVEForFixedLengthVectors(EVT VT) const	llvm::AArch64Subtarget	inline
VectorInsertExtractBaseCost	llvm::AArch64Subtarget	protected
VScaleForTuning	llvm::AArch64Subtarget	protected