llvm::AMDGPUDisassembler Member List

This is the complete list of members for llvm::AMDGPUDisassembler, including all inherited members.

AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)	llvm::AMDGPUDisassembler
CommentStream	llvm::MCDisassembler	mutable
convertDPP8Inst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertEXPInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertFMAanyK(MCInst &MI) const	llvm::AMDGPUDisassembler
convertMacDPPInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertMAIInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertMIMGInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertSDWAInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertTrue16OpSel(MCInst &MI) const	llvm::AMDGPUDisassembler
convertVINTERPInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertVOP3DPPInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertVOP3PDPPInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertVOPC64DPPInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertVOPCDPPInst(MCInst &MI) const	llvm::AMDGPUDisassembler
convertWMMAInst(MCInst &MI) const	llvm::AMDGPUDisassembler
createRegOperand(unsigned int RegId) const	llvm::AMDGPUDisassembler	inline
createRegOperand(unsigned RegClassID, unsigned Val) const	llvm::AMDGPUDisassembler	inline
createSRegOperand(unsigned SRegClassID, unsigned Val) const	llvm::AMDGPUDisassembler	inline
createVGPR16Operand(unsigned RegIdx, bool IsHi) const	llvm::AMDGPUDisassembler
decodeBoolReg(const MCInst &Inst, unsigned Val) const	llvm::AMDGPUDisassembler
decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const	llvm::AMDGPUDisassembler
decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const	llvm::AMDGPUDisassembler
decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const	llvm::AMDGPUDisassembler
decodeDpp8FI(unsigned Val) const	llvm::AMDGPUDisassembler
decodeIntImmed(unsigned Imm)	llvm::AMDGPUDisassembler	static
decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const	llvm::AMDGPUDisassembler
decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const	llvm::AMDGPUDisassembler
decodeLiteral64Constant() const	llvm::AMDGPUDisassembler
decodeLiteralConstant(const MCInstrDesc &Desc, const MCOperandInfo &OpDesc) const	llvm::AMDGPUDisassembler
decodeMandatoryLiteral64Constant(uint64_t Imm) const	llvm::AMDGPUDisassembler
decodeMandatoryLiteralConstant(unsigned Imm) const	llvm::AMDGPUDisassembler
decodeNonVGPRSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const	llvm::AMDGPUDisassembler
decodeSDWASrc(unsigned Width, unsigned Val) const	llvm::AMDGPUDisassembler
decodeSDWASrc16(unsigned Val) const	llvm::AMDGPUDisassembler
decodeSDWASrc32(unsigned Val) const	llvm::AMDGPUDisassembler
decodeSDWAVopcDst(unsigned Val) const	llvm::AMDGPUDisassembler
decodeSpecialReg32(unsigned Val) const	llvm::AMDGPUDisassembler
decodeSpecialReg64(unsigned Val) const	llvm::AMDGPUDisassembler
decodeSpecialReg96Plus(unsigned Val) const	llvm::AMDGPUDisassembler
decodeSplitBarrier(const MCInst &Inst, unsigned Val) const	llvm::AMDGPUDisassembler
decodeSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const	llvm::AMDGPUDisassembler
DecodeStatus enum name	llvm::MCDisassembler
decodeVersionImm(unsigned Imm) const	llvm::AMDGPUDisassembler
decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const	llvm::AMDGPUDisassembler
errOperand(unsigned V, const Twine &ErrMsg) const	llvm::AMDGPUDisassembler	inline
Fail enum value	llvm::MCDisassembler
getAgprClassId(unsigned Width) const	llvm::AMDGPUDisassembler
getContext() const	llvm::MCDisassembler	inline
getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override	llvm::AMDGPUDisassembler	virtual
getInstructionBundle(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const	llvm::MCDisassembler	inlinevirtual
getMCII() const	llvm::AMDGPUDisassembler	inline
getRegClassName(unsigned RegClassID) const	llvm::AMDGPUDisassembler
getSgprClassId(unsigned Width) const	llvm::AMDGPUDisassembler
getSubtargetInfo() const	llvm::MCDisassembler	inline
getTtmpClassId(unsigned Width) const	llvm::AMDGPUDisassembler
getTTmpIdx(unsigned Val) const	llvm::AMDGPUDisassembler
getVgprClassId(unsigned Width) const	llvm::AMDGPUDisassembler
hasArchitectedFlatScratch() const	llvm::AMDGPUDisassembler
hasKernargPreload() const	llvm::AMDGPUDisassembler
isBufferInstruction(const MCInst &MI) const	llvm::AMDGPUDisassembler
isGFX10() const	llvm::AMDGPUDisassembler
isGFX10Plus() const	llvm::AMDGPUDisassembler
isGFX11() const	llvm::AMDGPUDisassembler
isGFX11Plus() const	llvm::AMDGPUDisassembler
isGFX12() const	llvm::AMDGPUDisassembler
isGFX1250() const	llvm::AMDGPUDisassembler
isGFX12Plus() const	llvm::AMDGPUDisassembler
isGFX9() const	llvm::AMDGPUDisassembler
isGFX90A() const	llvm::AMDGPUDisassembler
isGFX9Plus() const	llvm::AMDGPUDisassembler
isMacDPP(MCInst &MI) const	llvm::AMDGPUDisassembler
isVI() const	llvm::AMDGPUDisassembler
MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)	llvm::MCDisassembler	inline
onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const override	llvm::AMDGPUDisassembler	virtual
setABIVersion(unsigned Version) override	llvm::AMDGPUDisassembler	virtual
setSymbolizer(std::unique_ptr< MCSymbolizer > Symzer)	llvm::MCDisassembler
SoftFail enum value	llvm::MCDisassembler
STI	llvm::MCDisassembler	protected
Success enum value	llvm::MCDisassembler
suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const	llvm::MCDisassembler	virtual
Symbolizer	llvm::MCDisassembler	protected
tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const	llvm::MCDisassembler
tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const	llvm::MCDisassembler
tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const	llvm::AMDGPUDisassembler
tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const	llvm::AMDGPUDisassembler
~AMDGPUDisassembler() override=default	llvm::AMDGPUDisassembler
~MCDisassembler()	llvm::MCDisassembler	virtual