llvm::MCSubtargetInfo Member List

This is the complete list of members for llvm::MCSubtargetInfo, including all inherited members.

ApplyFeatureFlag(StringRef FS)	llvm::MCSubtargetInfo
checkFeatures(StringRef FS) const	llvm::MCSubtargetInfo
ClearFeatureBitsTransitively(const FeatureBitset &FB)	llvm::MCSubtargetInfo
enableWritePrefetching() const	llvm::MCSubtargetInfo	virtual
getAllProcessorDescriptions() const	llvm::MCSubtargetInfo	inline
getAllProcessorFeatures() const	llvm::MCSubtargetInfo	inline
getCacheAssociativity(unsigned Level) const	llvm::MCSubtargetInfo	virtual
getCacheLineSize(unsigned Level) const	llvm::MCSubtargetInfo	virtual
getCacheLineSize() const	llvm::MCSubtargetInfo	inlinevirtual
getCacheSize(unsigned Level) const	llvm::MCSubtargetInfo	virtual
getCPU() const	llvm::MCSubtargetInfo	inline
getEnabledProcessorFeatures() const	llvm::MCSubtargetInfo
getFeatureBits() const	llvm::MCSubtargetInfo	inline
getFeatureString() const	llvm::MCSubtargetInfo	inline
getHwMode(enum HwModeType type=HwMode_Default) const	llvm::MCSubtargetInfo	inlinevirtual
getHwModeSet() const	llvm::MCSubtargetInfo	inlinevirtual
getInstrItineraryForCPU(StringRef CPU) const	llvm::MCSubtargetInfo
getMaxPrefetchIterationsAhead() const	llvm::MCSubtargetInfo	virtual
getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const	llvm::MCSubtargetInfo	virtual
getPrefetchDistance() const	llvm::MCSubtargetInfo	virtual
getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const	llvm::MCSubtargetInfo	inline
getReadAdvanceEntries(const MCSchedClassDesc &SC) const	llvm::MCSubtargetInfo	inline
getSchedModel() const	llvm::MCSubtargetInfo	inline
getSchedModelForCPU(StringRef CPU) const	llvm::MCSubtargetInfo
getTargetTriple() const	llvm::MCSubtargetInfo	inline
getTuneCPU() const	llvm::MCSubtargetInfo	inline
getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const	llvm::MCSubtargetInfo	inline
getWriteProcResBegin(const MCSchedClassDesc *SC) const	llvm::MCSubtargetInfo	inline
getWriteProcResEnd(const MCSchedClassDesc *SC) const	llvm::MCSubtargetInfo	inline
hasFeature(unsigned Feature) const	llvm::MCSubtargetInfo	inline
HwMode_Default enum value	llvm::MCSubtargetInfo
HwMode_EncodingInfo enum value	llvm::MCSubtargetInfo
HwMode_RegInfo enum value	llvm::MCSubtargetInfo
HwMode_ValueType enum value	llvm::MCSubtargetInfo
HwModeType enum name	llvm::MCSubtargetInfo
initInstrItins(InstrItineraryData &InstrItins) const	llvm::MCSubtargetInfo
InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS)	llvm::MCSubtargetInfo	protected
isCPUStringValid(StringRef CPU) const	llvm::MCSubtargetInfo	inlinevirtual
MCSubtargetInfo(const MCSubtargetInfo &)=default	llvm::MCSubtargetInfo
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< StringRef > PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)	llvm::MCSubtargetInfo
MCSubtargetInfo()=delete	llvm::MCSubtargetInfo
operator=(const MCSubtargetInfo &)=delete	llvm::MCSubtargetInfo
operator=(MCSubtargetInfo &&)=delete	llvm::MCSubtargetInfo
resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const	llvm::MCSubtargetInfo	inlinevirtual
setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)	llvm::MCSubtargetInfo
setFeatureBits(const FeatureBitset &FeatureBits_)	llvm::MCSubtargetInfo	inline
SetFeatureBitsTransitively(const FeatureBitset &FB)	llvm::MCSubtargetInfo
shouldPrefetchAddressSpace(unsigned AS) const	llvm::MCSubtargetInfo	virtual
ToggleFeature(uint64_t FB)	llvm::MCSubtargetInfo
ToggleFeature(const FeatureBitset &FB)	llvm::MCSubtargetInfo
ToggleFeature(StringRef FS)	llvm::MCSubtargetInfo
~MCSubtargetInfo()=default	llvm::MCSubtargetInfo	virtual