This is the complete list of members for llvm::MipsSEInstrInfo, including all inherited members.

adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override	llvm::MipsSEInstrInfo	virtual
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override	llvm::MipsInstrInfo
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr * > &BranchInstrs) const	llvm::MipsInstrInfo
BranchType enum name	llvm::MipsInstrInfo
BT_Cond enum value	llvm::MipsInstrInfo
BT_CondUncond enum value	llvm::MipsInstrInfo
BT_Indirect enum value	llvm::MipsInstrInfo
BT_NoBranch enum value	llvm::MipsInstrInfo
BT_None enum value	llvm::MipsInstrInfo
BT_Uncond enum value	llvm::MipsInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override	llvm::MipsSEInstrInfo
create(MipsSubtarget &STI)	llvm::MipsInstrInfo	static
decomposeMachineOperandsTargetFlags(unsigned TF) const override	llvm::MipsInstrInfo
describeLoadedValue(const MachineInstr &MI, Register Reg) const override	llvm::MipsInstrInfo
expandPostRAPseudo(MachineInstr &MI) const override	llvm::MipsSEInstrInfo
findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override	llvm::MipsInstrInfo
genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const	llvm::MipsInstrInfo
getEquivalentCompactForm(const MachineBasicBlock::iterator I) const	llvm::MipsInstrInfo
getInstSizeInBytes(const MachineInstr &MI) const override	llvm::MipsInstrInfo
GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const	llvm::MipsInstrInfo	protected
getNop() const override	llvm::MipsInstrInfo
getOppositeBranchOpc(unsigned Opc) const override	llvm::MipsSEInstrInfo	virtual
getRegisterInfo() const override	llvm::MipsSEInstrInfo	virtual
getSerializableDirectMachineOperandTargetFlags() const override	llvm::MipsInstrInfo
HasForbiddenSlot(const MachineInstr &MI) const	llvm::MipsInstrInfo
HasFPUDelaySlot(const MachineInstr &MI) const	llvm::MipsInstrInfo
HasLoadDelaySlot(const MachineInstr &MI) const	llvm::MipsInstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override	llvm::MipsInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override	llvm::MipsInstrInfo
insertNop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const	llvm::MipsInstrInfo
isAddImmediate(const MachineInstr &MI, Register Reg) const override	llvm::MipsInstrInfo
isAsCheapAsAMove(const MachineInstr &MI) const override	llvm::MipsInstrInfo
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override	llvm::MipsInstrInfo
isBranchWithImm(unsigned Opc) const override	llvm::MipsSEInstrInfo	virtual
isCopyInstrImpl(const MachineInstr &MI) const override	llvm::MipsSEInstrInfo	protected
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override	llvm::MipsSEInstrInfo
IsMfloOrMfhi(const MachineInstr &MI) const	llvm::MipsInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override	llvm::MipsSEInstrInfo
isZeroImm(const MachineOperand &op) const	llvm::MipsInstrInfo	protected
loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const	llvm::MipsSEInstrInfo
loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override	llvm::MipsSEInstrInfo	virtual
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override	llvm::MipsInstrInfo	inline
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)	llvm::MipsInstrInfo	explicit
MipsSEInstrInfo(const MipsSubtarget &STI)	llvm::MipsSEInstrInfo	explicit
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override	llvm::MipsInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override	llvm::MipsInstrInfo
SafeAfterMflo(const MachineInstr &MI) const	llvm::MipsInstrInfo
SafeInForbiddenSlot(const MachineInstr &MI) const	llvm::MipsInstrInfo
SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const	llvm::MipsInstrInfo
SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const	llvm::MipsInstrInfo
storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override	llvm::MipsSEInstrInfo	virtual
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override	llvm::MipsInstrInfo	inline
Subtarget	llvm::MipsInstrInfo	protected
UncondBrOpc	llvm::MipsInstrInfo	protected
verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override	llvm::MipsInstrInfo