llvm::RISCVInstrInfo Member List
This is the complete list of members for llvm::RISCVInstrInfo, including all inherited members.
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override | llvm::RISCVInstrInfo | |
| analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override | llvm::RISCVInstrInfo | |
| analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override | llvm::RISCVInstrInfo | |
| areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override | llvm::RISCVInstrInfo | |
| buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override | llvm::RISCVInstrInfo | |
| canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override | llvm::RISCVInstrInfo | |
| commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override | llvm::RISCVInstrInfo | |
| convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override | llvm::RISCVInstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override | llvm::RISCVInstrInfo | |
| copyPhysRegVector(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RegClass) const | llvm::RISCVInstrInfo | |
| createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override | llvm::RISCVInstrInfo | |
| decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::RISCVInstrInfo | |
| emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override | llvm::RISCVInstrInfo | |
| evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0, int64_t C1) | llvm::RISCVInstrInfo | static |
| finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override | llvm::RISCVInstrInfo | |
| findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override | llvm::RISCVInstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override | llvm::RISCVInstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const | llvm::RISCVInstrInfo | inline |
| genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const override | llvm::RISCVInstrInfo | |
| getBranchDestBlock(const MachineInstr &MI) const override | llvm::RISCVInstrInfo | |
| getCombinerObjective(unsigned Pattern) const override | llvm::RISCVInstrInfo | |
| getCondFromBranchOpc(unsigned Opc) | llvm::RISCVInstrInfo | static |
| getInstSizeInBytes(const MachineInstr &MI) const override | llvm::RISCVInstrInfo | |
| getInverseOpcode(unsigned Opcode) const override | llvm::RISCVInstrInfo | |
| getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override | llvm::RISCVInstrInfo | |
| getMachineCombinerTraceStrategy() const override | llvm::RISCVInstrInfo | |
| getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override | llvm::RISCVInstrInfo | |
| getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const | llvm::RISCVInstrInfo | |
| getNop() const override | llvm::RISCVInstrInfo | |
| getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override | llvm::RISCVInstrInfo | |
| getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MBBI, unsigned Flags) const override | llvm::RISCVInstrInfo | |
| getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const override | llvm::RISCVInstrInfo | |
| getSerializableDirectMachineOperandTargetFlags() const override | llvm::RISCVInstrInfo | |
| getSerializableMachineMemOperandTargetFlags() const override | llvm::RISCVInstrInfo | |
| getTailDuplicateSize(CodeGenOptLevel OptLevel) const override | llvm::RISCVInstrInfo | |
| hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override | llvm::RISCVInstrInfo | |
| hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const override | llvm::RISCVInstrInfo | |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override | llvm::RISCVInstrInfo | |
| insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override | llvm::RISCVInstrInfo | |
| insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override | llvm::RISCVInstrInfo | |
| isAddImmediate(const MachineInstr &MI, Register Reg) const override | llvm::RISCVInstrInfo | |
| isAsCheapAsAMove(const MachineInstr &MI) const override | llvm::RISCVInstrInfo | |
| isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override | llvm::RISCVInstrInfo | |
| isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override | llvm::RISCVInstrInfo | |
| isCopyInstrImpl(const MachineInstr &MI) const override | llvm::RISCVInstrInfo | |
| isFromLoadImm(const MachineRegisterInfo &MRI, const MachineOperand &Op, int64_t &Imm) | llvm::RISCVInstrInfo | static |
| isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override | llvm::RISCVInstrInfo | |
| isHighLatencyDef(int Opc) const override | llvm::RISCVInstrInfo | |
| isLdStSafeToPair(const MachineInstr &LdSt, const TargetRegisterInfo *TRI) | llvm::RISCVInstrInfo | static |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::RISCVInstrInfo | |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const override | llvm::RISCVInstrInfo | |
| isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override | llvm::RISCVInstrInfo | |
| isPairableLdStInstOpc(unsigned Opc) | llvm::RISCVInstrInfo | static |
| isReMaterializableImpl(const MachineInstr &MI) const override | llvm::RISCVInstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::RISCVInstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const override | llvm::RISCVInstrInfo | |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override | llvm::RISCVInstrInfo | |
| movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const | llvm::RISCVInstrInfo | |
| mulImm(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const | llvm::RISCVInstrInfo | |
| optimizeCondBranch(MachineInstr &MI) const override | llvm::RISCVInstrInfo | |
| optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override | llvm::RISCVInstrInfo | |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::RISCVInstrInfo | |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::RISCVInstrInfo | |
| RISCVInstrInfo(const RISCVSubtarget &STI) | llvm::RISCVInstrInfo | explicit |
| shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override | llvm::RISCVInstrInfo | inline |
| shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override | llvm::RISCVInstrInfo | |
| shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override | llvm::RISCVInstrInfo | |
| simplifyInstruction(MachineInstr &MI) const override | llvm::RISCVInstrInfo | |
| STI | llvm::RISCVInstrInfo | protected |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override | llvm::RISCVInstrInfo | |
| useMachineCombiner() const override | llvm::RISCVInstrInfo | inline |
| verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override | llvm::RISCVInstrInfo |
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