llvm::SIRegisterInfo Member List
This is the complete list of members for llvm::SIRegisterInfo, including all inherited members.
| addImplicitUsesForBlockCSRLoad(MachineInstrBuilder &MIB, Register BlockReg) const | llvm::SIRegisterInfo | |
| buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LiveRegUnits *LiveUnits=nullptr) const | llvm::SIRegisterInfo | |
| buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const | llvm::SIRegisterInfo | |
| eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override | llvm::SIRegisterInfo | |
| eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool SpillToPhysVGPRLane=false) const | llvm::SIRegisterInfo | |
| findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const | llvm::SIRegisterInfo | |
| findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const | llvm::SIRegisterInfo | |
| get32BitRegister(MCPhysReg Reg) const | llvm::SIRegisterInfo | |
| getAGPRClassForBitWidth(unsigned BitWidth) const | llvm::SIRegisterInfo | |
| getAlignedHighSGPRForRC(const MachineFunction &MF, const unsigned Align, const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | |
| getAlignedLo256VGPRClassForBitWidth(unsigned BitWidth) const | llvm::SIRegisterInfo | |
| getAllAGPRRegMask() const | llvm::SIRegisterInfo | |
| getAllAllocatableSRegMask() const | llvm::SIRegisterInfo | |
| getAllSGPR128(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| getAllSGPR32(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| getAllSGPR64(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| getAllVectorRegMask() const | llvm::SIRegisterInfo | |
| getAllVGPRRegMask() const | llvm::SIRegisterInfo | |
| getBaseRegister() const | llvm::SIRegisterInfo | |
| getBoolRC() const | llvm::SIRegisterInfo | inline |
| getCalleeSavedRegs(const MachineFunction *MF) const override | llvm::SIRegisterInfo | |
| getCalleeSavedRegsViaCopy(const MachineFunction *MF) const | llvm::SIRegisterInfo | |
| getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override | llvm::SIRegisterInfo | |
| getChannelFromSubReg(unsigned SubReg) const | llvm::SIRegisterInfo | inline |
| getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const | llvm::SIRegisterInfo | |
| getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override | llvm::SIRegisterInfo | |
| getCrossCopyRegClass(const TargetRegisterClass *RC) const override | llvm::SIRegisterInfo | |
| getCSRFirstUseCost() const override | llvm::SIRegisterInfo | inline |
| getEquivalentAGPRClass(const TargetRegisterClass *SRC) const | llvm::SIRegisterInfo | |
| getEquivalentSGPRClass(const TargetRegisterClass *VRC) const | llvm::SIRegisterInfo | |
| getEquivalentVGPRClass(const TargetRegisterClass *SRC) const | llvm::SIRegisterInfo | |
| getExec() const | llvm::SIRegisterInfo | |
| getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override | llvm::SIRegisterInfo | |
| getFrameRegister(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getHWRegIndex(MCRegister Reg) const | llvm::SIRegisterInfo | |
| getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getNoPreservedMask() const override | llvm::SIRegisterInfo | |
| getNumChannelsFromSubReg(unsigned SubReg) const | llvm::SIRegisterInfo | inline |
| getNumCoveredRegs(LaneBitmask LM) | llvm::SIRegisterInfo | inlinestatic |
| getNumUsedPhysRegs(const MachineRegisterInfo &MRI, const TargetRegisterClass &RC, bool IncludeCalls=true) const | llvm::SIRegisterInfo | |
| getPointerRegClass(unsigned Kind=0) const override | llvm::SIRegisterInfo | |
| getProperlyAlignedRC(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | |
| getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override | llvm::SIRegisterInfo | |
| getRegAsmName(MCRegister Reg) const override | llvm::SIRegisterInfo | |
| getRegClass(unsigned RCID) const | llvm::SIRegisterInfo | |
| getRegClassAlignmentNumBits(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | inline |
| getRegClassForBlockOp(const MachineFunction &MF) const | llvm::SIRegisterInfo | inline |
| getRegClassForOperandReg(const MachineRegisterInfo &MRI, const MachineOperand &MO) const | llvm::SIRegisterInfo | |
| getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const | llvm::SIRegisterInfo | |
| getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const | llvm::SIRegisterInfo | |
| getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const | llvm::SIRegisterInfo | inline |
| getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override | llvm::SIRegisterInfo | |
| getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const | llvm::SIRegisterInfo | |
| getRegUnitPressureSets(unsigned RegUnit) const override | llvm::SIRegisterInfo | |
| getReservedRegs(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getReturnAddressReg(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| getScratchInstrOffset(const MachineInstr *MI) const | llvm::SIRegisterInfo | |
| getSGPRClassForBitWidth(unsigned BitWidth) | llvm::SIRegisterInfo | static |
| getSubRegAlignmentNumBits(const TargetRegisterClass *RC, unsigned SubReg) const | llvm::SIRegisterInfo | |
| getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1) | llvm::SIRegisterInfo | static |
| getVCC() const | llvm::SIRegisterInfo | |
| getVectorSuperClassForBitWidth(unsigned BitWidth) const | llvm::SIRegisterInfo | |
| getVGPR64Class() const | llvm::SIRegisterInfo | |
| getVGPRClassForBitWidth(unsigned BitWidth) const | llvm::SIRegisterInfo | |
| getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getVRegFlagValue(StringRef Name) const override | llvm::SIRegisterInfo | inline |
| getWaveMaskRegClass() const | llvm::SIRegisterInfo | inline |
| hasAGPRs(const TargetRegisterClass *RC) | llvm::SIRegisterInfo | inlinestatic |
| hasBasePointer(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| hasSGPRs(const TargetRegisterClass *RC) | llvm::SIRegisterInfo | inlinestatic |
| hasVectorRegisters(const TargetRegisterClass *RC) | llvm::SIRegisterInfo | inlinestatic |
| hasVGPRs(const TargetRegisterClass *RC) | llvm::SIRegisterInfo | inlinestatic |
| isAGPR(const MachineRegisterInfo &MRI, Register Reg) const | llvm::SIRegisterInfo | |
| isAGPRClass(const TargetRegisterClass *RC) | llvm::SIRegisterInfo | inlinestatic |
| isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override | llvm::SIRegisterInfo | |
| isChainScratchRegister(Register VGPR) | llvm::SIRegisterInfo | static |
| isDivergentRegClass(const TargetRegisterClass *RC) const override | llvm::SIRegisterInfo | inline |
| isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override | llvm::SIRegisterInfo | |
| isProperlyAlignedRC(const TargetRegisterClass &RC) const | llvm::SIRegisterInfo | |
| isRegClassAligned(const TargetRegisterClass *RC, unsigned AlignNumBits) const | llvm::SIRegisterInfo | inline |
| isSGPRClass(const TargetRegisterClass *RC) | llvm::SIRegisterInfo | inlinestatic |
| isSGPRClassID(unsigned RCID) const | llvm::SIRegisterInfo | inline |
| isSGPRPhysReg(Register Reg) const | llvm::SIRegisterInfo | inline |
| isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const | llvm::SIRegisterInfo | |
| isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const override | llvm::SIRegisterInfo | |
| isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const | llvm::SIRegisterInfo | inline |
| isVectorSuperClass(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | inline |
| isVGPR(const MachineRegisterInfo &MRI, Register Reg) const | llvm::SIRegisterInfo | |
| isVGPRClass(const TargetRegisterClass *RC) | llvm::SIRegisterInfo | inlinestatic |
| isVGPRPhysReg(Register Reg) const | llvm::SIRegisterInfo | inline |
| isVSSuperClass(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | inline |
| materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override | llvm::SIRegisterInfo | |
| needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override | llvm::SIRegisterInfo | |
| opCanUseInlineConstant(unsigned OpType) const | llvm::SIRegisterInfo | |
| opCanUseLiteralConstant(unsigned OpType) const | llvm::SIRegisterInfo | |
| requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| requiresFrameIndexScavenging(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| requiresRegisterScavenging(const MachineFunction &Fn) const override | llvm::SIRegisterInfo | |
| requiresVirtualBaseRegisters(const MachineFunction &Fn) const override | llvm::SIRegisterInfo | |
| reservedPrivateSegmentBufferReg(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override | llvm::SIRegisterInfo | |
| restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const | llvm::SIRegisterInfo | |
| shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override | llvm::SIRegisterInfo | |
| shouldRealignStack(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| SIRegisterInfo(const GCNSubtarget &ST) | llvm::SIRegisterInfo | |
| spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const | llvm::SIRegisterInfo | |
| spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const | llvm::SIRegisterInfo | |
| spillSGPRToVGPR() const | llvm::SIRegisterInfo | inline |
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