| addrSinkUsingGEPs() const | llvm::TargetSubtargetInfo | inlinevirtual |
| adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const | llvm::TargetSubtargetInfo | inlinevirtual |
| AntiDepBreakMode typedef | llvm::TargetSubtargetInfo | |
| ApplyFeatureFlag(StringRef FS) | llvm::MCSubtargetInfo | |
| checkFeatures(StringRef FS) const | llvm::MCSubtargetInfo | |
| classifyGlobalFunctionReference(const GlobalValue *GV) const | llvm::TargetSubtargetInfo | inlinevirtual |
| ClearFeatureBitsTransitively(const FeatureBitset &FB) | llvm::MCSubtargetInfo | |
| enableAtomicExpand() const | llvm::TargetSubtargetInfo | virtual |
| enableEarlyIfConversion() const | llvm::TargetSubtargetInfo | inlinevirtual |
| enableIndirectBrExpand() const | llvm::TargetSubtargetInfo | virtual |
| enableJoinGlobalCopies() const | llvm::TargetSubtargetInfo | virtual |
| enableMachinePipeliner() const | llvm::TargetSubtargetInfo | inlinevirtual |
| enableMachineSchedDefaultSched() const | llvm::TargetSubtargetInfo | inlinevirtual |
| enableMachineScheduler() const | llvm::TargetSubtargetInfo | virtual |
| enablePostRAMachineScheduler() const | llvm::TargetSubtargetInfo | virtual |
| enablePostRAScheduler() const | llvm::TargetSubtargetInfo | virtual |
| enableRALocalReassignment(CodeGenOptLevel OptLevel) const | llvm::TargetSubtargetInfo | virtual |
| enableSpillageCopyElimination() const | llvm::TargetSubtargetInfo | inlinevirtual |
| enableSubRegLiveness() const | llvm::TargetSubtargetInfo | inlinevirtual |
| enableWindowScheduler() const | llvm::TargetSubtargetInfo | inlinevirtual |
| enableWritePrefetching() const | llvm::MCSubtargetInfo | virtual |
| getAllProcessorDescriptions() const | llvm::MCSubtargetInfo | inline |
| getAllProcessorFeatures() const | llvm::MCSubtargetInfo | inline |
| getAntiDepBreakMode() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getCacheAssociativity(unsigned Level) const | llvm::MCSubtargetInfo | virtual |
| getCacheLineSize(unsigned Level) const | llvm::MCSubtargetInfo | virtual |
| getCacheLineSize() const | llvm::MCSubtargetInfo | inlinevirtual |
| getCacheSize(unsigned Level) const | llvm::MCSubtargetInfo | virtual |
| getCallLowering() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getCPU() const | llvm::MCSubtargetInfo | inline |
| getCriticalPathRCs(RegClassVector &CriticalPathRCs) const | llvm::TargetSubtargetInfo | inlinevirtual |
| getCustomPBQPConstraints() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getDAGScheduler(CodeGenOptLevel) const | llvm::TargetSubtargetInfo | inlinevirtual |
| getEnabledProcessorFeatures() const | llvm::MCSubtargetInfo | |
| getFeatureBits() const | llvm::MCSubtargetInfo | inline |
| getFeatureString() const | llvm::MCSubtargetInfo | inline |
| getFrameLowering() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getHwMode(enum HwModeType type=HwMode_Default) const | llvm::MCSubtargetInfo | inlinevirtual |
| getHwModeSet() const | llvm::MCSubtargetInfo | inlinevirtual |
| getInlineAsmLowering() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getInstrInfo() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getInstrItineraryData() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getInstrItineraryForCPU(StringRef CPU) const | llvm::MCSubtargetInfo | |
| getInstructionSelector() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getLegalizerInfo() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getMacroFusions() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getMaxPrefetchIterationsAhead() const | llvm::MCSubtargetInfo | virtual |
| getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const | llvm::MCSubtargetInfo | virtual |
| getOptLevelToEnablePostRAScheduler() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const | llvm::TargetSubtargetInfo | inlinevirtual |
| getPrefetchDistance() const | llvm::MCSubtargetInfo | virtual |
| getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const | llvm::MCSubtargetInfo | inline |
| getReadAdvanceEntries(const MCSchedClassDesc &SC) const | llvm::MCSubtargetInfo | inline |
| getRegBankInfo() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getRegisterInfo() const =0 | llvm::TargetSubtargetInfo | pure virtual |
| getSchedModel() const | llvm::MCSubtargetInfo | inline |
| getSchedModelForCPU(StringRef CPU) const | llvm::MCSubtargetInfo | |
| getSelectionDAGInfo() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const | llvm::TargetSubtargetInfo | inlinevirtual |
| getTargetLowering() const | llvm::TargetSubtargetInfo | inlinevirtual |
| getTargetTriple() const | llvm::MCSubtargetInfo | inline |
| getTuneCPU() const | llvm::MCSubtargetInfo | inline |
| getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const | llvm::MCSubtargetInfo | inline |
| getWriteProcResBegin(const MCSchedClassDesc *SC) const | llvm::MCSubtargetInfo | inline |
| getWriteProcResEnd(const MCSchedClassDesc *SC) const | llvm::MCSubtargetInfo | inline |
| hasFeature(unsigned Feature) const | llvm::MCSubtargetInfo | inline |
| HwMode_Default enum value | llvm::MCSubtargetInfo | |
| HwMode_EncodingInfo enum value | llvm::MCSubtargetInfo | |
| HwMode_RegInfo enum value | llvm::MCSubtargetInfo | |
| HwMode_ValueType enum value | llvm::MCSubtargetInfo | |
| HwModeType enum name | llvm::MCSubtargetInfo | |
| ignoreCSRForAllocationOrder(const MachineFunction &MF, MCRegister PhysReg) const | llvm::TargetSubtargetInfo | inlinevirtual |
| initInstrItins(InstrItineraryData &InstrItins) const | llvm::MCSubtargetInfo | |
| InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS) | llvm::MCSubtargetInfo | protected |
| isCPUStringValid(StringRef CPU) const | llvm::MCSubtargetInfo | inlinevirtual |
| isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const | llvm::TargetSubtargetInfo | inlinevirtual |
| isOptimizableRegisterMove(const MachineInstr *MI) const | llvm::TargetSubtargetInfo | inlinevirtual |
| isRegisterReservedByUser(Register R) const | llvm::TargetSubtargetInfo | inlinevirtual |
| isXRaySupported() const | llvm::TargetSubtargetInfo | inlinevirtual |
| isZeroIdiom(const MachineInstr *MI, APInt &Mask) const | llvm::TargetSubtargetInfo | inlinevirtual |
| MCSubtargetInfo(const MCSubtargetInfo &)=default | llvm::MCSubtargetInfo | |
| MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< StringRef > PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | llvm::MCSubtargetInfo | |
| MCSubtargetInfo()=delete | llvm::MCSubtargetInfo | |
| mirFileLoaded(MachineFunction &MF) const | llvm::TargetSubtargetInfo | virtual |
| operator=(const TargetSubtargetInfo &)=delete | llvm::TargetSubtargetInfo | |
| llvm::MCSubtargetInfo::operator=(const MCSubtargetInfo &)=delete | llvm::MCSubtargetInfo | |
| llvm::MCSubtargetInfo::operator=(MCSubtargetInfo &&)=delete | llvm::MCSubtargetInfo | |
| overridePostRASchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const | llvm::TargetSubtargetInfo | inlinevirtual |
| overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const | llvm::TargetSubtargetInfo | inlinevirtual |
| RegClassVector typedef | llvm::TargetSubtargetInfo | |
| requiresDisjointEarlyClobberAndUndef() const | llvm::TargetSubtargetInfo | inlinevirtual |
| resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const | llvm::TargetSubtargetInfo | inlinevirtual |
| resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const | llvm::MCSubtargetInfo | inlinevirtual |
| setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) | llvm::MCSubtargetInfo | |
| setFeatureBits(const FeatureBitset &FeatureBits_) | llvm::MCSubtargetInfo | inline |
| SetFeatureBitsTransitively(const FeatureBitset &FB) | llvm::MCSubtargetInfo | |
| shouldPrefetchAddressSpace(unsigned AS) const | llvm::MCSubtargetInfo | virtual |
| TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< StringRef > PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | llvm::TargetSubtargetInfo | protected |
| TargetSubtargetInfo()=delete | llvm::TargetSubtargetInfo | |
| TargetSubtargetInfo(const TargetSubtargetInfo &)=delete | llvm::TargetSubtargetInfo | |
| ToggleFeature(uint64_t FB) | llvm::MCSubtargetInfo | |
| ToggleFeature(const FeatureBitset &FB) | llvm::MCSubtargetInfo | |
| ToggleFeature(StringRef FS) | llvm::MCSubtargetInfo | |
| useAA() const | llvm::TargetSubtargetInfo | virtual |
| useDFAforSMS() const | llvm::TargetSubtargetInfo | inlinevirtual |
| ~MCSubtargetInfo()=default | llvm::MCSubtargetInfo | virtual |
| ~TargetSubtargetInfo() override | llvm::TargetSubtargetInfo | |
1.14.0