This is the complete list of members for llvm::XtensaInstrInfo, including all inherited members.

adjustStackPtr(MCRegister SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const	llvm::XtensaInstrInfo
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override	llvm::XtensaInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override	llvm::XtensaInstrInfo
getBranchDestBlock(const MachineInstr &MI) const override	llvm::XtensaInstrInfo
getInstSizeInBytes(const MachineInstr &MI) const override	llvm::XtensaInstrInfo
getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode, int64_t offset) const	llvm::XtensaInstrInfo
getRegisterInfo() const	llvm::XtensaInstrInfo	inline
getSubtarget() const	llvm::XtensaInstrInfo	inline
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override	llvm::XtensaInstrInfo
insertBranchAtInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock TBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int BytesAdded) const	llvm::XtensaInstrInfo
insertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr I, int64_t offset, ArrayRef< MachineOperand > Cond, DebugLoc DL, int BytesAdded) const	llvm::XtensaInstrInfo
insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const override	llvm::XtensaInstrInfo
isBranch(const MachineBasicBlock::iterator &MI, SmallVectorImpl< MachineOperand > &Cond, const MachineOperand *&Target) const	llvm::XtensaInstrInfo
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override	llvm::XtensaInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override	llvm::XtensaInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override	llvm::XtensaInstrInfo
loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MCRegister *Reg, int64_t Value) const	llvm::XtensaInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override	llvm::XtensaInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override	llvm::XtensaInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override	llvm::XtensaInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override	llvm::XtensaInstrInfo
XtensaInstrInfo(const XtensaSubtarget &STI)	llvm::XtensaInstrInfo