LLVM 23.0.0git
AMDGPUInstructionSelector.h
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1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
17#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class TargetRegisterClass;
47
48class AMDGPUInstructionSelector final : public InstructionSelector {
49private:
50 MachineRegisterInfo *MRI;
51 const GCNSubtarget *Subtarget;
52
53public:
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
55 const AMDGPURegisterBankInfo &RBI,
56 const AMDGPUTargetMachine &TM);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
61 void setupMF(MachineFunction &MF, GISelValueTracking *VT,
62 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
67 SmallVector<unsigned, 2> SgprParts;
68 SmallVector<unsigned, 2> VgprParts;
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectCOPY_SCC_VCC(MachineInstr &I) const;
91 bool selectCOPY_VCC_SCC(MachineInstr &I) const;
92 bool selectReadAnyLane(MachineInstr &I) const;
93 bool selectPHI(MachineInstr &I) const;
94 bool selectG_TRUNC(MachineInstr &I) const;
95 bool selectG_SZA_EXT(MachineInstr &I) const;
96 bool selectG_FPEXT(MachineInstr &I) const;
97 bool selectG_FNEG(MachineInstr &I) const;
98 bool selectG_FABS(MachineInstr &I) const;
99 bool selectG_AND_OR_XOR(MachineInstr &I) const;
100 bool selectG_ADD_SUB(MachineInstr &I) const;
101 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
103 bool selectG_EXTRACT(MachineInstr &I) const;
104 bool selectG_FMA_FMAD(MachineInstr &I) const;
105 bool selectG_MERGE_VALUES(MachineInstr &I) const;
106 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
107 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
108 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
109 bool selectG_INSERT(MachineInstr &I) const;
110 bool selectG_SBFX_UBFX(MachineInstr &I) const;
111
112 bool selectInterpP1F16(MachineInstr &MI) const;
113 bool selectWritelane(MachineInstr &MI) const;
114 bool selectDivScale(MachineInstr &MI) const;
115 bool selectIntrinsicCmp(MachineInstr &MI) const;
116 bool selectBallot(MachineInstr &I) const;
117 bool selectRelocConstant(MachineInstr &I) const;
118 bool selectGroupStaticSize(MachineInstr &I) const;
119 bool selectReturnAddress(MachineInstr &I) const;
120 bool selectG_INTRINSIC(MachineInstr &I) const;
121
122 bool selectEndCfIntrinsic(MachineInstr &MI) const;
123 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
126 bool selectInitWholeWave(MachineInstr &MI) const;
127 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
128
129 bool selectImageIntrinsic(MachineInstr &MI,
130 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
132 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
133 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
134 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
135 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
136 SmallVectorImpl<GEPInfo> &AddrInfo) const;
137
138 void initM0(MachineInstr &I) const;
139 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
140 bool selectG_SELECT(MachineInstr &I) const;
141 bool selectG_BRCOND(MachineInstr &I) const;
142 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
143 bool selectG_PTRMASK(MachineInstr &I) const;
144 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
145 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
146 bool selectBufferLoadLds(MachineInstr &MI) const;
147 bool selectGlobalLoadLds(MachineInstr &MI) const;
148 bool selectTensorLoadStore(MachineInstr &MI, Intrinsic::ID IID) const;
149 bool selectBVHIntersectRayIntrinsic(MachineInstr &I) const;
150 bool selectSMFMACIntrin(MachineInstr &I) const;
151 bool selectPermlaneSwapIntrin(MachineInstr &I, Intrinsic::ID IntrID) const;
152 bool selectWaveAddress(MachineInstr &I) const;
153 bool selectBITOP3(MachineInstr &I) const;
154 bool selectStackRestore(MachineInstr &MI) const;
155 bool selectNamedBarrierInit(MachineInstr &I, Intrinsic::ID IID) const;
156 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
157 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
158 bool selectSGetBarrierState(MachineInstr &I, Intrinsic::ID IID) const;
159 bool selectSBarrierLeave(MachineInstr &I) const;
160 bool selectWaveShuffleIntrin(MachineInstr &I) const;
161
162 std::pair<Register, unsigned> selectVOP3ModsImpl(Register Src,
163 bool IsCanonicalizing = true,
164 bool AllowAbs = true,
165 bool OpSel = false) const;
166 std::pair<Register, unsigned> selectVOP3PModsF32Impl(Register Src) const;
167
168 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
169 MachineOperand Root, MachineInstr *InsertPt,
170 bool ForceVGPR = false) const;
171
172 InstructionSelector::ComplexRendererFns
173 selectVCSRC(MachineOperand &Root) const;
174
175 InstructionSelector::ComplexRendererFns
176 selectVSRC0(MachineOperand &Root) const;
177
178 InstructionSelector::ComplexRendererFns
179 selectVOP3Mods0(MachineOperand &Root) const;
180 InstructionSelector::ComplexRendererFns
181 selectVOP3BMods0(MachineOperand &Root) const;
182 InstructionSelector::ComplexRendererFns
183 selectVOP3OMods(MachineOperand &Root) const;
184 InstructionSelector::ComplexRendererFns
185 selectVOP3Mods(MachineOperand &Root) const;
186 InstructionSelector::ComplexRendererFns
187 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
188 InstructionSelector::ComplexRendererFns
189 selectVOP3BMods(MachineOperand &Root) const;
190
191 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
192
193 std::pair<Register, unsigned>
194 selectVOP3PModsImpl(Register RootReg, const MachineRegisterInfo &MRI,
195 bool IsDOT = false) const;
196 InstructionSelector::ComplexRendererFns
197 selectVOP3PRetHelper(MachineOperand &Root, bool IsDOT = false) const;
198
199 InstructionSelector::ComplexRendererFns
200 selectVOP3PMods(MachineOperand &Root) const;
201
202 InstructionSelector::ComplexRendererFns
203 selectVOP3PModsDOT(MachineOperand &Root) const;
204 InstructionSelector::ComplexRendererFns
205 selectVOP3PNoModsDOT(MachineOperand &Root) const;
206 InstructionSelector::ComplexRendererFns
207 selectVOP3PModsF32(MachineOperand &Root) const;
208 InstructionSelector::ComplexRendererFns
209 selectVOP3PNoModsF32(MachineOperand &Root) const;
210
211 InstructionSelector::ComplexRendererFns
212 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
213
214 InstructionSelector::ComplexRendererFns
215 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
216 InstructionSelector::ComplexRendererFns
217 selectWMMAModsF16Neg(MachineOperand &Root) const;
218 InstructionSelector::ComplexRendererFns
219 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
220 InstructionSelector::ComplexRendererFns
221 selectWMMAVISrc(MachineOperand &Root) const;
222 InstructionSelector::ComplexRendererFns
223 selectSWMMACIndex8(MachineOperand &Root) const;
224 InstructionSelector::ComplexRendererFns
225 selectSWMMACIndex16(MachineOperand &Root) const;
226 InstructionSelector::ComplexRendererFns
227 selectSWMMACIndex32(MachineOperand &Root) const;
228
229 InstructionSelector::ComplexRendererFns
230 selectVOP3OpSelMods(MachineOperand &Root) const;
231
232 InstructionSelector::ComplexRendererFns
233 selectVINTERPMods(MachineOperand &Root) const;
234 InstructionSelector::ComplexRendererFns
235 selectVINTERPModsHi(MachineOperand &Root) const;
236
237 bool selectScaleOffset(MachineOperand &Root, Register &Offset,
238 bool IsSigned) const;
239 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
240 int64_t *Offset, bool *ScaleOffset) const;
241 InstructionSelector::ComplexRendererFns
242 selectSmrdImm(MachineOperand &Root) const;
243 InstructionSelector::ComplexRendererFns
244 selectSmrdImm32(MachineOperand &Root) const;
245 InstructionSelector::ComplexRendererFns
246 selectSmrdSgpr(MachineOperand &Root) const;
247 InstructionSelector::ComplexRendererFns
248 selectSmrdSgprImm(MachineOperand &Root) const;
249
250 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
251 uint64_t FlatVariant) const;
252
253 InstructionSelector::ComplexRendererFns
254 selectFlatOffset(MachineOperand &Root) const;
255 InstructionSelector::ComplexRendererFns
256 selectGlobalOffset(MachineOperand &Root) const;
257 InstructionSelector::ComplexRendererFns
258 selectScratchOffset(MachineOperand &Root) const;
259
260 InstructionSelector::ComplexRendererFns
261 selectGlobalSAddr(MachineOperand &Root, unsigned CPolBits,
262 bool NeedIOffset = true) const;
263 InstructionSelector::ComplexRendererFns
264 selectGlobalSAddr(MachineOperand &Root) const;
265 InstructionSelector::ComplexRendererFns
266 selectGlobalSAddrCPol(MachineOperand &Root) const;
267 InstructionSelector::ComplexRendererFns
268 selectGlobalSAddrCPolM0(MachineOperand &Root) const;
269 InstructionSelector::ComplexRendererFns
270 selectGlobalSAddrGLC(MachineOperand &Root) const;
271 InstructionSelector::ComplexRendererFns
272 selectGlobalSAddrNoIOffset(MachineOperand &Root) const;
273 InstructionSelector::ComplexRendererFns
274 selectGlobalSAddrNoIOffsetM0(MachineOperand &Root) const;
275
276 InstructionSelector::ComplexRendererFns
277 selectScratchSAddr(MachineOperand &Root) const;
278 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
279 uint64_t ImmOffset) const;
280 InstructionSelector::ComplexRendererFns
281 selectScratchSVAddr(MachineOperand &Root) const;
282
283 InstructionSelector::ComplexRendererFns
284 selectMUBUFScratchOffen(MachineOperand &Root) const;
285 InstructionSelector::ComplexRendererFns
286 selectMUBUFScratchOffset(MachineOperand &Root) const;
287
288 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
289 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
290 unsigned Size) const;
291 bool isFlatScratchBaseLegal(Register Addr) const;
292 bool isFlatScratchBaseLegalSV(Register Addr) const;
293 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
294
295 std::pair<Register, unsigned>
296 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
297 InstructionSelector::ComplexRendererFns
298 selectDS1Addr1Offset(MachineOperand &Root) const;
299
300 InstructionSelector::ComplexRendererFns
301 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
302
303 InstructionSelector::ComplexRendererFns
304 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
305
306 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
307 unsigned size) const;
308 InstructionSelector::ComplexRendererFns
309 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
310
311 std::tuple<Register, int64_t, bool>
312 getPtrBaseWithConstantOffset(Register Root,
313 const MachineRegisterInfo &MRI) const;
314
315 // Parse out a chain of up to two g_ptr_add instructions.
316 // g_ptr_add (n0, _)
317 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
318 struct MUBUFAddressData {
319 Register N0, N2, N3;
320 int64_t Offset = 0;
321 };
322
323 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
324
325 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
326 Register &SOffset, int64_t &ImmOffset) const;
327
328 MUBUFAddressData parseMUBUFAddress(Register Src) const;
329
330 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
331 Register &RSrcReg, Register &SOffset,
332 int64_t &Offset) const;
333
334 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
335 Register &SOffset, int64_t &Offset) const;
336
337 InstructionSelector::ComplexRendererFns
338 selectBUFSOffset(MachineOperand &Root) const;
339
340 InstructionSelector::ComplexRendererFns
341 selectMUBUFAddr64(MachineOperand &Root) const;
342
343 InstructionSelector::ComplexRendererFns
344 selectMUBUFOffset(MachineOperand &Root) const;
345
346 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
347 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
348 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
349
350 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
351 bool &Matched) const;
352 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
353 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
354
355 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
356 int OpIdx = -1) const;
357
358 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
359 int OpIdx) const;
360 void renderZextBoolTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
361 int OpIdx) const;
362
363 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
364 int OpIdx) const;
365
366 void renderSrcAndDstSelToOpSelXForm_0_0(MachineInstrBuilder &MIB,
367 const MachineInstr &MI,
368 int OpIdx) const;
369
370 void renderSrcAndDstSelToOpSelXForm_0_1(MachineInstrBuilder &MIB,
371 const MachineInstr &MI,
372 int OpIdx) const;
373
374 void renderSrcAndDstSelToOpSelXForm_1_0(MachineInstrBuilder &MIB,
375 const MachineInstr &MI,
376 int OpIdx) const;
377
378 void renderSrcAndDstSelToOpSelXForm_1_1(MachineInstrBuilder &MIB,
379 const MachineInstr &MI,
380 int OpIdx) const;
381
382 void renderDstSelToOpSelXForm(MachineInstrBuilder &MIB,
383 const MachineInstr &MI, int OpIdx) const;
384
385 void renderSrcSelToOpSelXForm(MachineInstrBuilder &MIB,
386 const MachineInstr &MI, int OpIdx) const;
387
388 void renderSrcAndDstSelToOpSelXForm_2_0(MachineInstrBuilder &MIB,
389 const MachineInstr &MI,
390 int OpIdx) const;
391
392 void renderDstSelToOpSel3XFormXForm(MachineInstrBuilder &MIB,
393 const MachineInstr &MI, int OpIdx) const;
394
395 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
396 int OpIdx) const;
397
398 void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
399 int OpIdx) const;
400
401 void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
402 int OpIdx) const {
403 renderBitcastFPImm(MIB, MI, OpIdx);
404 }
405 void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
406 int OpIdx) const {
407 renderBitcastFPImm(MIB, MI, OpIdx);
408 }
409
410 void renderCountTrailingOnesImm(MachineInstrBuilder &MIB,
411 const MachineInstr &MI, int OpIdx) const;
412 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
413 int OpIdx) const;
414 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
415 int OpIdx) const;
416 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
417 int OpIdx) const;
418
419 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
420 int OpIdx) const;
421
422 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
423 int OpIdx) const;
424
425 void renderRoundMode(MachineInstrBuilder &MIB, const MachineInstr &MI,
426 int OpIdx) const;
427
428 void renderVOP3PModsNeg(MachineInstrBuilder &MIB, const MachineInstr &MI,
429 int OpIdx) const;
430 void renderVOP3PModsNegs(MachineInstrBuilder &MIB, const MachineInstr &MI,
431 int OpIdx) const;
432 void renderVOP3PModsNegAbs(MachineInstrBuilder &MIB, const MachineInstr &MI,
433 int OpIdx) const;
434
435 void renderPrefetchLoc(MachineInstrBuilder &MIB, const MachineInstr &MI,
436 int OpIdx) const;
437
438 void renderScaledMAIIntrinsicOperand(MachineInstrBuilder &MIB,
439 const MachineInstr &MI, int OpIdx) const;
440
441 bool isInlineImmediate(const APInt &Imm) const;
442 bool isInlineImmediate(const APFloat &Imm) const;
443
444 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
445 // shift amount operand's `ShAmtBits` bits is unneeded.
446 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
447
448 /// Match a zero extend from a 32-bit value to 64-bits.
449 Register matchZeroExtendFromS32(Register Reg) const;
450 /// Match a sign extend from a 32-bit value to 64-bits.
451 Register matchSignExtendFromS32(Register Reg) const;
452 /// Match a zero extend from a 32-bit value to 64-bits, or \p Reg itself if it
453 /// is 32-bit.
454 Register matchZeroExtendFromS32OrS32(Register Reg) const;
455 /// Match a sign extend from a 32-bit value to 64-bits, or \p Reg itself if it
456 /// is 32-bit.
457 Register matchSignExtendFromS32OrS32(Register Reg) const;
458 /// Match either sign or zero extend depending on the \p IsSigned from a
459 /// 32-bit value to 64-bits, or \p Reg itself if it is 32-bit.
460 Register matchExtendFromS32OrS32(Register Reg, bool IsSigned) const;
461 /// Match an any extend from a 32-bit value to 64-bit.
462 Register matchAnyExtendFromS32(Register Reg) const;
463
464 const SIInstrInfo &TII;
465 const SIRegisterInfo &TRI;
466 const AMDGPURegisterBankInfo &RBI;
467 const AMDGPUTargetMachine &TM;
468 const GCNSubtarget &STI;
469#define GET_GLOBALISEL_PREDICATES_DECL
470#define AMDGPUSubtarget GCNSubtarget
471#include "AMDGPUGenGlobalISel.inc"
472#undef GET_GLOBALISEL_PREDICATES_DECL
473#undef AMDGPUSubtarget
474
475#define GET_GLOBALISEL_TEMPORARIES_DECL
476#include "AMDGPUGenGlobalISel.inc"
477#undef GET_GLOBALISEL_TEMPORARIES_DECL
478};
479
480} // End llvm namespace.
481#endif
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2126
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2127
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
OpIdx
MachineInstr unsigned OpIdx
Definition NVPTXPrologEpilogPass.cpp:56
P
#define P(N)
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
Definition AMDGPUInstructionSelector.cpp:43
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition AMDGPUInstructionSelector.cpp:4362
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelValueTracking *VT, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
Definition AMDGPUInstructionSelector.cpp:59
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition BlockFrequencyInfo.h:38
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:676
llvm::GIMatchTableExecutor::ComplexRendererFns
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition GIMatchTableExecutor.h:622
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition MachineIRBuilder.h:237
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:73
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:53
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition ProfileSummaryInfo.h:42
llvm::RegisterBank
This class implements the register bank concept.
Definition RegisterBank.h:29
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition SmallVector.h:576
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1205
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:242
uint64_t
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:532
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1669
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