Directory dependency graph for AMDGPU:

Directories
	AsmParser
	Disassembler
	MCA
	MCTargetDesc
	TargetInfo
	Utils

Files
	AMDGPU.h
	AMDGPUAliasAnalysis.cpp
	This is the AMGPU address space based alias analysis pass.
	AMDGPUAliasAnalysis.h
	This is the AMGPU address space based alias analysis pass.
	AMDGPUAlwaysInlinePass.cpp
	This pass marks all internal functions as always_inline and creates duplicates of all other functions and marks the duplicates as always_inline.
	AMDGPUAnnotateUniformValues.cpp
	This pass adds amdgpu.uniform metadata to IR values so this information can be used during instruction selection.
	AMDGPUArgumentUsageInfo.cpp
	AMDGPUArgumentUsageInfo.h
	AMDGPUAsanInstrumentation.cpp
	AMDGPUAsanInstrumentation.h
	AMDGPUAsmPrinter.cpp
	The AMDGPUAsmPrinter is used to print both assembly string and also binary code.
	AMDGPUAsmPrinter.h
	AMDGPU Assembly printer class.
	AMDGPUAtomicOptimizer.cpp
	This pass optimizes atomic operations by using a single lane of a wavefront to perform the atomic operation, thus reducing contention on that memory location.
	AMDGPUAttributor.cpp
	AMDGPUBarrierLatency.cpp
	AMDGPUBarrierLatency.h
	AMDGPUCallLowering.cpp
	This file implements the lowering of LLVM calls to machine code calls for GlobalISel.
	AMDGPUCallLowering.h
	This file describes how to lower LLVM calls to machine code calls.
	AMDGPUCodeGenPrepare.cpp
	This pass does misc.
	AMDGPUCombinerHelper.cpp
	AMDGPUCombinerHelper.h
	This contains common combine transformations that may be used in a combine pass.
	AMDGPUCtorDtorLowering.cpp
	This pass creates a unified init and fini kernel with the required metadata.
	AMDGPUCtorDtorLowering.h
	AMDGPUExportClustering.cpp
	AMDGPUExportClustering.h
	AMDGPUExportKernelRuntimeHandles.cpp
	AMDGPUExportKernelRuntimeHandles.h
	AMDGPUFrameLowering.cpp
	AMDGPUFrameLowering.h
	Interface to describe a layout of a stack frame on an AMDGPU target.
	AMDGPUGlobalISelDivergenceLowering.cpp
	GlobalISel pass that selects divergent i1 phis as lane mask phis.
	AMDGPUGlobalISelUtils.cpp
	AMDGPUGlobalISelUtils.h
	AMDGPUHSAMetadataStreamer.cpp
	AMDGPU HSA Metadata Streamer.
	AMDGPUHSAMetadataStreamer.h
	AMDGPU HSA Metadata Streamer.
	AMDGPUIGroupLP.cpp
	AMDGPUIGroupLP.h
	AMDGPUImageIntrinsicOptimizer.cpp
	AMDGPUInsertDelayAlu.cpp
	Insert s_delay_alu instructions to avoid stalls on GFX11+.
	AMDGPUInstCombineIntrinsic.cpp
	AMDGPUInstrInfo.cpp
	Implementation of the TargetInstrInfo class that is common to all AMD GPUs.
	AMDGPUInstrInfo.h
	Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
	AMDGPUInstructionSelector.cpp
	This file implements the targeting of the InstructionSelector class for AMDGPU.
	AMDGPUInstructionSelector.h
	This file declares the targeting of the InstructionSelector class for AMDGPU.
	AMDGPUISelDAGToDAG.cpp
	Defines an instruction selector for the AMDGPU target.
	AMDGPUISelDAGToDAG.h
	Defines an instruction selector for the AMDGPU target.
	AMDGPUISelLowering.cpp
	This is the parent TargetLowering class for hardware code gen targets.
	AMDGPUISelLowering.h
	Interface definition of the TargetLowering class that is common to all AMD GPUs.
	AMDGPULaneMaskUtils.h
	AMDGPULateCodeGenPrepare.cpp
	This pass does misc.
	AMDGPULegalizerInfo.cpp
	This file implements the targeting of the Machinelegalizer class for AMDGPU.
	AMDGPULegalizerInfo.h
	This file declares the targeting of the Machinelegalizer class for AMDGPU.
	AMDGPULibCalls.cpp
	This file does AMD library function optimizations.
	AMDGPULibFunc.cpp
	AMDGPULibFunc.h
	AMDGPULowerBufferFatPointers.cpp
	AMDGPULowerIntrinsics.cpp
	AMDGPULowerKernelArguments.cpp
	AMDGPULowerKernelAttributes.cpp
	AMDGPULowerModuleLDSPass.cpp
	AMDGPULowerVGPREncoding.cpp
	Lower VGPRs above first 256 on gfx1250.
	AMDGPULowerVGPREncoding.h
	AMDGPUMachineFunction.cpp
	AMDGPUMachineFunction.h
	AMDGPUMachineModuleInfo.cpp
	AMDGPU Machine Module Info.
	AMDGPUMachineModuleInfo.h
	AMDGPU Machine Module Info.
	AMDGPUMacroFusion.cpp
	AMDGPUMacroFusion.h
	AMDGPUMarkLastScratchLoad.cpp
	AMDGPUMCInstLower.cpp
	Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
	AMDGPUMCInstLower.h
	Header of lower AMDGPU MachineInstrs to their corresponding MCInst.
	AMDGPUMCResourceInfo.cpp
	MC infrastructure to propagate the function level resource usage info.
	AMDGPUMCResourceInfo.h
	MC infrastructure to propagate the function level resource usage info.
	AMDGPUMemoryUtils.cpp
	AMDGPUMemoryUtils.h
	AMDGPUMIRFormatter.cpp
	Implementation of AMDGPU overrides of MIRFormatter.
	AMDGPUMIRFormatter.h
	AMDGPU specific overrides of MIRFormatter.
	AMDGPUPerfHintAnalysis.cpp
	Analyzes if a function potentially memory bound and if a kernel kernel may benefit from limiting number of waves to reduce cache thrashing.
	AMDGPUPerfHintAnalysis.h
	Analyzes if a function potentially memory bound and if a kernel kernel may benefit from limiting number of waves to reduce cache thrashing.
	AMDGPUPostLegalizerCombiner.cpp
	AMDGPUPreLegalizerCombiner.cpp
	AMDGPUPreloadKernArgProlog.cpp
	AMDGPUPreloadKernArgProlog.h
	AMDGPUPreloadKernelArguments.cpp
	AMDGPUPrepareAGPRAlloc.cpp
	AMDGPUPrepareAGPRAlloc.h
	AMDGPUPrintfRuntimeBinding.cpp
	AMDGPUPromoteAlloca.cpp
	AMDGPUPromoteKernelArguments.cpp
	AMDGPUPTNote.h
	Enums and constants for AMDGPU PT_NOTE sections.
	AMDGPURegBankCombiner.cpp
	AMDGPURegBankLegalize.cpp
	AMDGPURegBankLegalizeHelper.cpp
	AMDGPURegBankLegalizeHelper.h
	AMDGPURegBankLegalizeRules.cpp
	AMDGPURegBankLegalizeRules.h
	AMDGPURegBankSelect.cpp
	AMDGPURegisterBankInfo.cpp
	This file implements the targeting of the RegisterBankInfo class for AMDGPU.
	AMDGPURegisterBankInfo.h
	This file declares the targeting of the RegisterBankInfo class for AMDGPU.
	AMDGPURemoveIncompatibleFunctions.cpp
	This pass replaces all uses of functions that use GPU features incompatible with the current GPU with null then deletes the function.
	AMDGPURemoveIncompatibleFunctions.h
	AMDGPUReserveWWMRegs.cpp
	This pass should be invoked at the end of wwm-regalloc pipeline.
	AMDGPUReserveWWMRegs.h
	AMDGPUResourceUsageAnalysis.cpp
	Analyzes how many registers and other resources are used by functions.
	AMDGPUResourceUsageAnalysis.h
	Analyzes how many registers and other resources are used by functions.
	AMDGPURewriteAGPRCopyMFMA.cpp
	AMDGPURewriteOutArguments.cpp
	AMDGPURewriteUndefForPHI.cpp
	AMDGPUSelectionDAGInfo.cpp
	AMDGPUSelectionDAGInfo.h
	AMDGPUSetWavePriority.cpp
	Pass to temporarily raise the wave priority beginning the start of the shader function until its last VMEM instructions to allow younger waves to issue their VMEM instructions as well.
	AMDGPUSplitModule.cpp
	AMDGPUSplitModule.h
	AMDGPUSubtarget.cpp
	Implements the AMDGPU specific subclass of TargetSubtarget.
	AMDGPUSubtarget.h
	Base class for AMDGPU specific classes of TargetSubtarget.
	AMDGPUSwLowerLDS.cpp
	AMDGPUTargetMachine.cpp
	This file contains both AMDGPU target machine and the CodeGen pass builder.
	AMDGPUTargetMachine.h
	The AMDGPU TargetMachine interface definition for hw codegen targets.
	AMDGPUTargetObjectFile.cpp
	AMDGPUTargetObjectFile.h
	This file declares the AMDGPU-specific subclass of TargetLoweringObjectFile.
	AMDGPUTargetTransformInfo.cpp
	AMDGPUTargetTransformInfo.h
	This file a TargetTransformInfoImplBase conforming object specific to the AMDGPU target machine.
	AMDGPUUniformIntrinsicCombine.cpp
	This pass simplifies certain intrinsic calls when the arguments are uniform.
	AMDGPUUnifyDivergentExitNodes.cpp
	AMDGPUUnifyDivergentExitNodes.h
	AMDGPUWaitSGPRHazards.cpp
	Insert s_wait_alu instructions to mitigate SGPR read hazards on GFX12.
	AMDGPUWaitSGPRHazards.h
	AMDKernelCodeT.h
	GCNCreateVOPD.cpp
	Combine VALU pairs into VOPD instructions Only works on wave32 Has register requirements, we reject creating VOPD if the requirements are not met.
	GCNDPPCombine.cpp
	GCNDPPCombine.h
	GCNHazardRecognizer.cpp
	GCNHazardRecognizer.h
	GCNILPSched.cpp
	GCNIterativeScheduler.cpp
	This file implements the class GCNIterativeScheduler.
	GCNIterativeScheduler.h
	This file defines the class GCNIterativeScheduler, which uses an iterative approach to find a best schedule for GCN architecture.
	GCNMinRegStrategy.cpp
	This file defines and implements the class GCNMinRegScheduler, which implements an experimental, simple scheduler whose main goal is to learn ways about consuming less possible registers for a region.
	GCNNSAReassign.cpp
	Try to reassign registers on GFX10+ from non-sequential to sequential in NSA image instructions.
	GCNNSAReassign.h
	GCNPreRALongBranchReg.cpp
	GCNPreRALongBranchReg.h
	GCNPreRAOptimizations.cpp
	This pass combines split register tuple initialization into a single pseudo:
	GCNPreRAOptimizations.h
	GCNRegPressure.cpp
	This file implements the GCNRegPressure class.
	GCNRegPressure.h
	This file defines the GCNRegPressure class, which tracks registry pressure by bookkeeping number of SGPR/VGPRs used, weights for large SGPR/VGPRs.
	GCNRewritePartialRegUses.cpp
	RenameIndependentSubregs pass leaves large partially used super registers, for example: undef %0.sub4:VReg_1024 = ... %0.sub5:VReg_1024 = ... %0.sub6:VReg_1024 = ... %0.sub7:VReg_1024 = ... use %0.sub4_sub5_sub6_sub7 use %0.sub6_sub7.
	GCNRewritePartialRegUses.h
	GCNSchedStrategy.cpp
	This contains a MachineSchedStrategy implementation for maximizing wave occupancy on GCN hardware.
	GCNSchedStrategy.h
	GCNSubtarget.cpp
	Implements the GCN specific subclass of TargetSubtarget.
	GCNSubtarget.h
	AMD GCN specific subclass of TargetSubtarget.
	GCNVOPDUtils.cpp
	GCNVOPDUtils.h
	R600.h
	R600AsmPrinter.cpp
	The R600AsmPrinter is used to print both assembly string and also binary code.
	R600AsmPrinter.h
	R600 Assembly printer class.
	R600ClauseMergePass.cpp
	R600EmitClauseMarker pass emits CFAlu instruction in a conservative manner.
	R600ControlFlowFinalizer.cpp
	This pass compute turns all control flow pseudo instructions into native one computing their address on the fly; it also sets STACK_SIZE info.
	R600Defines.h
	R600EmitClauseMarkers.cpp
	Add CF_ALU.
	R600ExpandSpecialInstrs.cpp
	Vector, Reduction, and Cube instructions need to fill the entire instruction group to work correctly.
	R600FrameLowering.cpp
	R600FrameLowering.h
	R600InstrInfo.cpp
	R600 Implementation of TargetInstrInfo.
	R600InstrInfo.h
	Interface definition for R600InstrInfo.
	R600ISelDAGToDAG.cpp
	Defines an instruction selector for the R600 subtarget.
	R600ISelLowering.cpp
	Custom DAG lowering for R600.
	R600ISelLowering.h
	R600 DAG Lowering interface definition.
	R600MachineCFGStructurizer.cpp
	R600MachineFunctionInfo.cpp
	R600MachineFunctionInfo.h
	R600MachineScheduler.cpp
	R600 Machine Scheduler interface.
	R600MachineScheduler.h
	R600 Machine Scheduler interface.
	R600MCInstLower.cpp
	Code to lower R600 MachineInstrs to their corresponding MCInst.
	R600OpenCLImageTypeLoweringPass.cpp
	This pass resolves calls to OpenCL image attribute, image resource ID and sampler resource ID getter functions.
	R600OptimizeVectorRegisters.cpp
	This pass merges inputs of swizzeable instructions into vector sharing common data and/or have enough undef subreg using swizzle abilities.
	R600Packetizer.cpp
	This pass implements instructions packetization for R600.
	R600RegisterInfo.cpp
	R600 implementation of the TargetRegisterInfo class.
	R600RegisterInfo.h
	Interface definition for R600RegisterInfo.
	R600Subtarget.cpp
	Implements the R600 specific subclass of TargetSubtarget.
	R600Subtarget.h
	AMDGPU R600 specific subclass of TargetSubtarget.
	R600TargetMachine.cpp
	This file contains both AMDGPU-R600 target machine and the CodeGen pass builder.
	R600TargetMachine.h
	The AMDGPU TargetMachine interface definition for hw codegen targets.
	R600TargetTransformInfo.cpp
	R600TargetTransformInfo.h
	This file a TargetTransformInfoImplBase conforming object specific to the R600 target machine.
	SIAnnotateControlFlow.cpp
	Annotates the control flow with hardware specific intrinsics.
	SIDefines.h
	SIFixSGPRCopies.cpp
	Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this:
	SIFixSGPRCopies.h
	SIFixVGPRCopies.cpp
	Add implicit use of exec to vector register copies.
	SIFixVGPRCopies.h
	SIFoldOperands.cpp
	SIFoldOperands.h
	SIFormMemoryClauses.cpp
	SIFormMemoryClauses.h
	SIFrameLowering.cpp
	SIFrameLowering.h
	SIInsertHardClauses.cpp
	Insert s_clause instructions to form hard clauses.
	SIInsertWaitcnts.cpp
	Insert wait instructions for memory reads and writes.
	SIInstrInfo.cpp
	SI Implementation of TargetInstrInfo.
	SIInstrInfo.h
	Interface definition for SIInstrInfo.
	SIISelLowering.cpp
	Custom DAG lowering for SI.
	SIISelLowering.h
	SI DAG Lowering interface definition.
	SILateBranchLowering.cpp
	This pass mainly lowers early terminate pseudo instructions.
	SILoadStoreOptimizer.cpp
	SILoadStoreOptimizer.h
	SILowerControlFlow.cpp
	This pass lowers the pseudo control flow instructions to real machine instructions.
	SILowerControlFlow.h
	SILowerI1Copies.cpp
	SILowerI1Copies.h
	Interface definition of the PhiLoweringHelper class that implements lane mask merging algorithm for divergent i1 phis.
	SILowerSGPRSpills.cpp
	SILowerSGPRSpills.h
	SILowerWWMCopies.cpp
	Lowering the WWM_COPY instructions for various register classes.
	SILowerWWMCopies.h
	SIMachineFunctionInfo.cpp
	SIMachineFunctionInfo.h
	SIMachineScheduler.cpp
	SI Machine Scheduler interface.
	SIMachineScheduler.h
	SI Machine Scheduler interface.
	SIMemoryLegalizer.cpp
	Memory legalizer - implements memory model.
	SIModeRegister.cpp
	This pass inserts changes to the Mode register settings as required.
	SIModeRegisterDefaults.cpp
	SIModeRegisterDefaults.h
	SIOptimizeExecMasking.cpp
	SIOptimizeExecMasking.h
	SIOptimizeExecMaskingPreRA.cpp
	This pass performs exec mask handling peephole optimizations which needs to be done before register allocation to reduce register pressure.
	SIOptimizeExecMaskingPreRA.h
	SIOptimizeVGPRLiveRange.cpp
	This pass tries to remove unnecessary VGPR live ranges in divergent if-else structures and waterfall loops.
	SIOptimizeVGPRLiveRange.h
	SIPeepholeSDWA.cpp
	SIPeepholeSDWA.h
	SIPostRABundler.cpp
	This pass creates bundles of memory instructions to protect adjacent loads and stores from being rescheduled apart from each other post-RA.
	SIPostRABundler.h
	SIPreAllocateWWMRegs.cpp
	Pass to pre-allocated WWM registers.
	SIPreAllocateWWMRegs.h
	SIPreEmitPeephole.cpp
	This pass performs the peephole optimizations before code emission.
	SIProgramInfo.cpp
	The SIProgramInfo tracks resource usage and hardware flags for kernels and entry functions.
	SIProgramInfo.h
	Defines struct to track resource usage and hardware flags for kernels and entry functions.
	SIRegisterInfo.cpp
	SI implementation of the TargetRegisterInfo class.
	SIRegisterInfo.h
	Interface definition for SIRegisterInfo.
	SIShrinkInstructions.cpp
	SIShrinkInstructions.h
	SIWholeQuadMode.cpp
	This pass adds instructions to enable whole quad mode (strict or non-strict) for pixel shaders, and strict whole wavefront mode for all programs.
	SIWholeQuadMode.h

Directories

Files