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LLVM 22.0.0git
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Try to reassign registers on GFX10+ from non-sequential to sequential in NSA image instructions. More...
#include "GCNNSAReassign.h"#include "AMDGPU.h"#include "GCNSubtarget.h"#include "SIMachineFunctionInfo.h"#include "SIRegisterInfo.h"#include "llvm/ADT/Statistic.h"#include "llvm/CodeGen/LiveIntervals.h"#include "llvm/CodeGen/LiveRegMatrix.h"#include "llvm/CodeGen/MachineFunctionPass.h"#include "llvm/CodeGen/VirtRegMap.h"#include "llvm/InitializePasses.h"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "amdgpu-nsa-reassign" |
Functions | |
| STATISTIC (NumNSAInstructions, "Number of NSA instructions with non-sequential address found") | |
| STATISTIC (NumNSAConverted, "Number of NSA instructions changed to sequential") | |
| INITIALIZE_PASS_BEGIN (GCNNSAReassignLegacy, DEBUG_TYPE, "GCN NSA Reassign", false, false) INITIALIZE_PASS_END(GCNNSAReassignLegacy | |
Variables | |
| DEBUG_TYPE | |
| GCN NSA | Reassign |
| GCN NSA | false |
Try to reassign registers on GFX10+ from non-sequential to sequential in NSA image instructions.
Later SIShrinkInstructions pass will replace NSA with sequential versions where possible.
Definition in file GCNNSAReassign.cpp.
| #define DEBUG_TYPE "amdgpu-nsa-reassign" |
Definition at line 30 of file GCNNSAReassign.cpp.
| INITIALIZE_PASS_BEGIN | ( | GCNNSAReassignLegacy | , |
| DEBUG_TYPE | , | ||
| "GCN NSA Reassign" | , | ||
| false | , | ||
| false | ) |
References DEBUG_TYPE, and INITIALIZE_PASS_DEPENDENCY.
| STATISTIC | ( | NumNSAConverted | , |
| "Number of NSA instructions changed to sequential" | ) |
| STATISTIC | ( | NumNSAInstructions | , |
| "Number of NSA instructions with non-sequential address found" | ) |
| DEBUG_TYPE |
Definition at line 108 of file GCNNSAReassign.cpp.
| GCN NSA false |
Definition at line 108 of file GCNNSAReassign.cpp.
| GCN NSA Reassign |
Definition at line 108 of file GCNNSAReassign.cpp.