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LLVM 22.0.0git
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#include "HexagonISelDAGToDAG.h"#include "Hexagon.h"#include "HexagonISelLowering.h"#include "HexagonMachineFunctionInfo.h"#include "HexagonTargetMachine.h"#include "llvm/CodeGen/FunctionLoweringInfo.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/SelectionDAGISel.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/IntrinsicsHexagon.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "HexagonGenDAGISel.inc"Go to the source code of this file.
Namespaces | |
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
Macros | |
| #define | DEBUG_TYPE "hexagon-isel" |
| #define | PASS_NAME "Hexagon DAG->DAG Pattern Instruction Selection" |
| #define | GET_DAGISEL_BODY HexagonDAGToDAGISel |
Functions | |
| FunctionPass * | llvm::createHexagonISelDag (HexagonTargetMachine &TM, CodeGenOptLevel OptLevel) |
| createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG, ready for instruction scheduling. | |
| static bool | isMemOPCandidate (SDNode *I, SDNode *U) |
| static bool | isOpcodeHandled (const SDNode *N) |
| static unsigned | getPowerOf2Factor (SDValue Val) |
| static bool | willShiftRightEliminate (SDValue V, unsigned Amount) |
| static bool | isTargetConstant (const SDValue &V) |
Variables | |
| static cl::opt< bool > | EnableAddressRebalancing ("isel-rebalance-addr", cl::Hidden, cl::init(true), cl::desc("Rebalance address calculation trees to improve " "instruction selection")) |
| static cl::opt< bool > | RebalanceOnlyForOptimizations ("rebalance-only-opt", cl::Hidden, cl::init(false), cl::desc("Rebalance address tree only if this allows optimizations")) |
| static cl::opt< bool > | RebalanceOnlyImbalancedTrees ("rebalance-only-imbal", cl::Hidden, cl::init(false), cl::desc("Rebalance address tree only if it is imbalanced")) |
| static cl::opt< bool > | CheckSingleUse ("hexagon-isel-su", cl::Hidden, cl::init(true), cl::desc("Enable checking of SDNode's single-use status")) |
| #define DEBUG_TYPE "hexagon-isel" |
Definition at line 27 of file HexagonISelDAGToDAG.cpp.
| #define GET_DAGISEL_BODY HexagonDAGToDAGISel |
Definition at line 55 of file HexagonISelDAGToDAG.cpp.
| #define PASS_NAME "Hexagon DAG->DAG Pattern Instruction Selection" |
Definition at line 28 of file HexagonISelDAGToDAG.cpp.
Definition at line 1966 of file HexagonISelDAGToDAG.cpp.
References llvm::CallingConv::C, llvm::APInt::countr_zero(), llvm::dyn_cast(), llvm::APInt::getBoolValue(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isa(), llvm::ISD::MUL, and llvm::ISD::SHL.
Definition at line 1081 of file HexagonISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::cast(), llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), I, Opc, llvm::ISD::OR, S1, llvm::ISD::SUB, and llvm::SDNode::user_begin().
Definition at line 1780 of file HexagonISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::isa(), llvm::ISD::MUL, N, and llvm::ISD::SHL.
Definition at line 2030 of file HexagonISelDAGToDAG.cpp.
References llvm::HexagonISD::CONST32, and llvm::HexagonISD::CONST32_GP.
Definition at line 1989 of file HexagonISelDAGToDAG.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, getNode(), llvm::isa(), llvm::ISD::MUL, and llvm::ISD::SHL.
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Referenced by llvm::HexagonDAGToDAGISel::PreprocessISelDAG().
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