LLVM 23.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandCCOpToCMov(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI);
51 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI, unsigned Opcode);
53 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI);
57 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61 bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MBBI);
63#ifndef NDEBUG
64 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
65 unsigned Size = 0;
66 for (auto &MBB : MF)
67 for (auto &MI : MBB)
68 Size += TII->getInstSizeInBytes(MI);
69 return Size;
70 }
71#endif
72};
73
74char RISCVExpandPseudo::ID = 0;
75
76bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
77 STI = &MF.getSubtarget<RISCVSubtarget>();
78 TII = STI->getInstrInfo();
79
80#ifndef NDEBUG
81 const unsigned OldSize = getInstSizeInBytes(MF);
82#endif
83
84 bool Modified = false;
85 for (auto &MBB : MF)
86 Modified |= expandMBB(MBB);
87
88#ifndef NDEBUG
89 const unsigned NewSize = getInstSizeInBytes(MF);
90 assert(OldSize >= NewSize);
91#endif
92 return Modified;
93}
94
95bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
96 bool Modified = false;
97
98 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
99 while (MBBI != E) {
100 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
101 Modified |= expandMI(MBB, MBBI, NMBBI);
102 MBBI = NMBBI;
103 }
104
105 return Modified;
106}
107
108bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MBBI,
110 MachineBasicBlock::iterator &NextMBBI) {
111 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
112 // expanded instructions for each pseudo is correct in the Size field of the
113 // tablegen definition for the pseudo.
114 switch (MBBI->getOpcode()) {
115 case RISCV::PseudoMV_FPR16INX:
116 return expandMV_FPR16INX(MBB, MBBI);
117 case RISCV::PseudoMV_FPR32INX:
118 return expandMV_FPR32INX(MBB, MBBI);
119 case RISCV::PseudoRV32ZdinxSD:
120 return expandRV32ZdinxStore(MBB, MBBI);
121 case RISCV::PseudoRV32ZdinxLD:
122 return expandRV32ZdinxLoad(MBB, MBBI);
123 case RISCV::PseudoCCMOVGPRNoX0:
124 case RISCV::PseudoCCMOVGPR:
125 case RISCV::PseudoCCADD:
126 case RISCV::PseudoCCSUB:
127 case RISCV::PseudoCCAND:
128 case RISCV::PseudoCCOR:
129 case RISCV::PseudoCCXOR:
130 case RISCV::PseudoCCMAX:
131 case RISCV::PseudoCCMAXU:
132 case RISCV::PseudoCCMIN:
133 case RISCV::PseudoCCMINU:
134 case RISCV::PseudoCCMUL:
135 case RISCV::PseudoCCLUI:
136 case RISCV::PseudoCCQC_E_LB:
137 case RISCV::PseudoCCQC_E_LH:
138 case RISCV::PseudoCCQC_E_LW:
139 case RISCV::PseudoCCQC_E_LHU:
140 case RISCV::PseudoCCQC_E_LBU:
141 case RISCV::PseudoCCLB:
142 case RISCV::PseudoCCLH:
143 case RISCV::PseudoCCLW:
144 case RISCV::PseudoCCLHU:
145 case RISCV::PseudoCCLBU:
146 case RISCV::PseudoCCLWU:
147 case RISCV::PseudoCCLD:
148 case RISCV::PseudoCCQC_LI:
149 case RISCV::PseudoCCQC_E_LI:
150 case RISCV::PseudoCCADDW:
151 case RISCV::PseudoCCSUBW:
152 case RISCV::PseudoCCSLL:
153 case RISCV::PseudoCCSRL:
154 case RISCV::PseudoCCSRA:
155 case RISCV::PseudoCCADDI:
156 case RISCV::PseudoCCSLLI:
157 case RISCV::PseudoCCSRLI:
158 case RISCV::PseudoCCSRAI:
159 case RISCV::PseudoCCANDI:
160 case RISCV::PseudoCCORI:
161 case RISCV::PseudoCCXORI:
162 case RISCV::PseudoCCSLLW:
163 case RISCV::PseudoCCSRLW:
164 case RISCV::PseudoCCSRAW:
165 case RISCV::PseudoCCADDIW:
166 case RISCV::PseudoCCSLLIW:
167 case RISCV::PseudoCCSRLIW:
168 case RISCV::PseudoCCSRAIW:
169 case RISCV::PseudoCCANDN:
170 case RISCV::PseudoCCORN:
171 case RISCV::PseudoCCXNOR:
172 case RISCV::PseudoCCNDS_BFOS:
173 case RISCV::PseudoCCNDS_BFOZ:
174 return expandCCOp(MBB, MBBI, NextMBBI);
175 case RISCV::PseudoVMCLR_M_B1:
176 case RISCV::PseudoVMCLR_M_B2:
177 case RISCV::PseudoVMCLR_M_B4:
178 case RISCV::PseudoVMCLR_M_B8:
179 case RISCV::PseudoVMCLR_M_B16:
180 case RISCV::PseudoVMCLR_M_B32:
181 case RISCV::PseudoVMCLR_M_B64:
182 // vmclr.m vd => vmxor.mm vd, vd, vd
183 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
184 case RISCV::PseudoVMSET_M_B1:
185 case RISCV::PseudoVMSET_M_B2:
186 case RISCV::PseudoVMSET_M_B4:
187 case RISCV::PseudoVMSET_M_B8:
188 case RISCV::PseudoVMSET_M_B16:
189 case RISCV::PseudoVMSET_M_B32:
190 case RISCV::PseudoVMSET_M_B64:
191 // vmset.m vd => vmxnor.mm vd, vd, vd
192 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
193 case RISCV::PseudoReadVLENBViaVSETVLIX0:
194 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
195 }
196
197 return false;
198}
199
200bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MBBI,
202 MachineBasicBlock::iterator &NextMBBI) {
203 // First try expanding to a Conditional Move rather than a branch+mv
204 if (expandCCOpToCMov(MBB, MBBI))
205 return true;
206
207 MachineFunction *MF = MBB.getParent();
208 MachineInstr &MI = *MBBI;
209 DebugLoc DL = MI.getDebugLoc();
210
211 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
212 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
213
214 MF->insert(++MBB.getIterator(), TrueBB);
215 MF->insert(++TrueBB->getIterator(), MergeBB);
216
217 // We want to copy the "true" value only when the branch is executed.
218 // The SDNodeXform is responsible for the inversion.
219 unsigned BranchOpCode =
220 MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
221
222 // Insert branch instruction.
223 BuildMI(MBB, MBBI, DL, TII->get(BranchOpCode))
224 .add(MI.getOperand(MI.getNumExplicitOperands() - 2))
225 .add(MI.getOperand(MI.getNumExplicitOperands() - 1))
226 .addMBB(MergeBB);
227
228 Register DestReg = MI.getOperand(0).getReg();
229 assert(MI.getOperand(1).getReg() == DestReg);
230
231 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
232 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
233 // Add MV.
234 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
235 .add(MI.getOperand(2))
236 .addImm(0);
237 } else {
238 unsigned NewOpc;
239 // clang-format off
240 switch (MI.getOpcode()) {
241 default:
242 llvm_unreachable("Unexpected opcode!");
243 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
244 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
245 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
246 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
247 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
248 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
249 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
250 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
251 case RISCV::PseudoCCMAX: NewOpc = RISCV::MAX; break;
252 case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
253 case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
254 case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
255 case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
256 case RISCV::PseudoCCLUI: NewOpc = RISCV::LUI; break;
257 case RISCV::PseudoCCQC_E_LB: NewOpc = RISCV::QC_E_LB; break;
258 case RISCV::PseudoCCQC_E_LH: NewOpc = RISCV::QC_E_LH; break;
259 case RISCV::PseudoCCQC_E_LW: NewOpc = RISCV::QC_E_LW; break;
260 case RISCV::PseudoCCQC_E_LHU: NewOpc = RISCV::QC_E_LHU; break;
261 case RISCV::PseudoCCQC_E_LBU: NewOpc = RISCV::QC_E_LBU; break;
262 case RISCV::PseudoCCLB: NewOpc = RISCV::LB; break;
263 case RISCV::PseudoCCLH: NewOpc = RISCV::LH; break;
264 case RISCV::PseudoCCLW: NewOpc = RISCV::LW; break;
265 case RISCV::PseudoCCLHU: NewOpc = RISCV::LHU; break;
266 case RISCV::PseudoCCLBU: NewOpc = RISCV::LBU; break;
267 case RISCV::PseudoCCLWU: NewOpc = RISCV::LWU; break;
268 case RISCV::PseudoCCLD: NewOpc = RISCV::LD; break;
269 case RISCV::PseudoCCQC_LI: NewOpc = RISCV::QC_LI; break;
270 case RISCV::PseudoCCQC_E_LI: NewOpc = RISCV::QC_E_LI; break;
271 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
272 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
273 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
274 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
275 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
276 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
277 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
278 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
279 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
280 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
281 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
282 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
283 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
284 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
285 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
286 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
287 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
288 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
289 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
290 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
291 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
292 }
293 // clang-format on
294
295 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
296 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
297 .add(MI.getOperand(2))
298 .add(MI.getOperand(3))
299 .add(MI.getOperand(4));
300 } else if (NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI ||
301 NewOpc == RISCV::QC_E_LI) {
302 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg).add(MI.getOperand(2));
303 } else {
304 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
305 .add(MI.getOperand(2))
306 .add(MI.getOperand(3));
307 }
308 }
309
310 TrueBB->addSuccessor(MergeBB);
311
312 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
313 MergeBB->transferSuccessors(&MBB);
314
315 MBB.addSuccessor(TrueBB);
316 MBB.addSuccessor(MergeBB);
317
318 NextMBBI = MBB.end();
319 MI.eraseFromParent();
320
321 // Make sure live-ins are correctly attached to this new basic block.
322 LivePhysRegs LiveRegs;
323 computeAndAddLiveIns(LiveRegs, *TrueBB);
324 computeAndAddLiveIns(LiveRegs, *MergeBB);
325
326 return true;
327}
328
329bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
330 MachineBasicBlock::iterator MBBI) {
331 MachineInstr &MI = *MBBI;
332 DebugLoc DL = MI.getDebugLoc();
333
334 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
335 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
336 return false;
337
338 if (!STI->hasVendorXqcicm())
339 return false;
340
341 MachineOperand &LHS = MI.getOperand(MI.getNumExplicitOperands() - 2);
342 MachineOperand &RHS = MI.getOperand(MI.getNumExplicitOperands() - 1);
343
344 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
345 if (LHS.getReg() == RISCV::X0 || MI.getOperand(1).getReg() == RISCV::X0 ||
346 MI.getOperand(2).getReg() == RISCV::X0)
347 return false;
348
349 // Use branch opcode to select appropriate Xqcicm instruction
350 unsigned BCC = MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
351 std::optional<unsigned> CMovRegOpcode;
352 unsigned CMovImmOpcode;
353 switch (BCC) {
354 default:
355 return false; // Unhandled branch opcodes
356 case RISCV::BNE:
357 CMovRegOpcode = RISCV::QC_MVEQ;
358 CMovImmOpcode = RISCV::QC_MVEQI;
359 break;
360 case RISCV::BEQ:
361 CMovRegOpcode = RISCV::QC_MVNE;
362 CMovImmOpcode = RISCV::QC_MVNEI;
363 break;
364 case RISCV::BGE:
365 CMovRegOpcode = RISCV::QC_MVLT;
366 CMovImmOpcode = RISCV::QC_MVLTI;
367 break;
368 case RISCV::BLT:
369 CMovRegOpcode = RISCV::QC_MVGE;
370 CMovImmOpcode = RISCV::QC_MVGEI;
371 break;
372 case RISCV::BGEU:
373 CMovRegOpcode = RISCV::QC_MVLTU;
374 CMovImmOpcode = RISCV::QC_MVLTUI;
375 break;
376 case RISCV::BLTU:
377 CMovRegOpcode = RISCV::QC_MVGEU;
378 CMovImmOpcode = RISCV::QC_MVGEUI;
379 break;
380 case RISCV::QC_BEQI:
381 CMovImmOpcode = RISCV::QC_MVEQI;
382 break;
383 case RISCV::QC_BNEI:
384 CMovImmOpcode = RISCV::QC_MVNEI;
385 break;
386 case RISCV::QC_BLTI:
387 CMovImmOpcode = RISCV::QC_MVLTI;
388 break;
389 case RISCV::QC_BGEI:
390 CMovImmOpcode = RISCV::QC_MVGEI;
391 break;
392 case RISCV::QC_BLTUI:
393 CMovImmOpcode = RISCV::QC_MVLTUI;
394 break;
395 case RISCV::QC_BGEUI:
396 CMovImmOpcode = RISCV::QC_MVGEUI;
397 break;
398 }
399
400 if (RHS.isImm() && isInt<5>(RHS.getImm())) {
401 // $dst = PseudoCCMOVGPR $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
402 // $dst = PseudoCCMOVGPRNoX0 $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
403 // =>
404 // $dst = QC_MVccI $falsev (=$dst), $lhs, $rhs_imm, $truev
405 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
406 .addDef(MI.getOperand(0).getReg())
407 .addReg(MI.getOperand(1).getReg())
408 .addReg(LHS.getReg())
409 .add(RHS)
410 .addReg(MI.getOperand(2).getReg());
411
412 MI.eraseFromParent();
413 return true;
414 }
415
416 if (RHS.getReg() == RISCV::X0) {
417 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, X0
418 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, X0
419 // =>
420 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
421 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
422 .addDef(MI.getOperand(0).getReg())
423 .addReg(MI.getOperand(1).getReg())
424 .addReg(LHS.getReg())
425 .addImm(0)
426 .addReg(MI.getOperand(2).getReg());
427
428 MI.eraseFromParent();
429 return true;
430 }
431
432 if (!CMovRegOpcode)
433 return false;
434
435 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, $rhs
436 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, $rhs
437 // =>
438 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
439 BuildMI(MBB, MBBI, DL, TII->get(*CMovRegOpcode))
440 .addDef(MI.getOperand(0).getReg())
441 .addReg(MI.getOperand(1).getReg())
442 .addReg(LHS.getReg())
443 .addReg(RHS.getReg())
444 .addReg(MI.getOperand(2).getReg());
445 MI.eraseFromParent();
446 return true;
447}
448
449bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
450 MachineBasicBlock::iterator MBBI,
451 unsigned Opcode) {
452 DebugLoc DL = MBBI->getDebugLoc();
453 Register DstReg = MBBI->getOperand(0).getReg();
454 const MCInstrDesc &Desc = TII->get(Opcode);
455 BuildMI(MBB, MBBI, DL, Desc, DstReg)
456 .addReg(DstReg, RegState::Undef)
457 .addReg(DstReg, RegState::Undef);
458 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
459 return true;
460}
461
462bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
463 MachineBasicBlock::iterator MBBI) {
464 DebugLoc DL = MBBI->getDebugLoc();
465 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
466 Register DstReg = TRI->getMatchingSuperReg(
467 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
468 Register SrcReg = TRI->getMatchingSuperReg(
469 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
470
471 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
472 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
473 .addImm(0);
474
475 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
476 return true;
477}
478
479bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
480 MachineBasicBlock::iterator MBBI) {
481 DebugLoc DL = MBBI->getDebugLoc();
482 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
483 Register DstReg = TRI->getMatchingSuperReg(
484 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
485 Register SrcReg = TRI->getMatchingSuperReg(
486 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
487
488 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
489 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
490 .addImm(0);
491
492 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
493 return true;
494}
495
496// This function expands the PseudoRV32ZdinxSD for storing a double-precision
497// floating-point value into memory by generating an equivalent instruction
498// sequence for RV32.
499bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
500 MachineBasicBlock::iterator MBBI) {
501 DebugLoc DL = MBBI->getDebugLoc();
502 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
503 Register Lo =
504 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
505 Register Hi =
506 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
507 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
508 Hi = RISCV::X0;
509
510 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
511 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
512 .addReg(MBBI->getOperand(1).getReg())
513 .add(MBBI->getOperand(2));
514
515 MachineInstrBuilder MIBHi;
516 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
517 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
518 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
519 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
520 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
521 .add(MBBI->getOperand(1))
522 .add(MBBI->getOperand(2));
523 } else {
524 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
525 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
526 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
527 .add(MBBI->getOperand(1))
528 .addImm(MBBI->getOperand(2).getImm() + 4);
529 }
530
531 MachineFunction *MF = MBB.getParent();
532 SmallVector<MachineMemOperand *> NewLoMMOs;
533 SmallVector<MachineMemOperand *> NewHiMMOs;
534 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
535 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
536 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
537 }
538 MIBLo.setMemRefs(NewLoMMOs);
539 MIBHi.setMemRefs(NewHiMMOs);
540
541 MBBI->eraseFromParent();
542 return true;
543}
544
545// This function expands PseudoRV32ZdinxLoad for loading a double-precision
546// floating-point value from memory into an equivalent instruction sequence for
547// RV32.
548bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
549 MachineBasicBlock::iterator MBBI) {
550 DebugLoc DL = MBBI->getDebugLoc();
551 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
552 Register Lo =
553 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
554 Register Hi =
555 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
556 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
557
558 MachineInstrBuilder MIBLo, MIBHi;
559
560 // If the register of operand 1 is equal to the Lo register, then swap the
561 // order of loading the Lo and Hi statements.
562 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
563 // Order: Lo, Hi
564 if (!IsOp1EqualToLo) {
565 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
566 .addReg(MBBI->getOperand(1).getReg())
567 .add(MBBI->getOperand(2));
568 }
569
570 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
571 auto Offset = MBBI->getOperand(2).getOffset();
572 assert(Offset % 8 == 0);
573 MBBI->getOperand(2).setOffset(Offset + 4);
574 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
575 .addReg(MBBI->getOperand(1).getReg())
576 .add(MBBI->getOperand(2));
577 MBBI->getOperand(2).setOffset(Offset);
578 } else {
579 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
580 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
581 .addReg(MBBI->getOperand(1).getReg())
582 .addImm(MBBI->getOperand(2).getImm() + 4);
583 }
584
585 // Order: Hi, Lo
586 if (IsOp1EqualToLo) {
587 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
588 .addReg(MBBI->getOperand(1).getReg())
589 .add(MBBI->getOperand(2));
590 }
591
592 MachineFunction *MF = MBB.getParent();
593 SmallVector<MachineMemOperand *> NewLoMMOs;
594 SmallVector<MachineMemOperand *> NewHiMMOs;
595 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
596 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
597 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
598 }
599 MIBLo.setMemRefs(NewLoMMOs);
600 MIBHi.setMemRefs(NewHiMMOs);
601
602 MBBI->eraseFromParent();
603 return true;
604}
605
606bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
607 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
608 DebugLoc DL = MBBI->getDebugLoc();
609 Register Dst = MBBI->getOperand(0).getReg();
610 unsigned Mul = MBBI->getOperand(1).getImm();
611 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
612 unsigned VTypeImm = RISCVVType::encodeVTYPE(
613 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
614
615 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
616 .addReg(Dst, RegState::Define)
617 .addReg(RISCV::X0, RegState::Kill)
618 .addImm(VTypeImm);
619
620 MBBI->eraseFromParent();
621 return true;
622}
623
624class RISCVPreRAExpandPseudo : public MachineFunctionPass {
625public:
626 const RISCVSubtarget *STI;
627 const RISCVInstrInfo *TII;
628 static char ID;
629
630 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
631
632 bool runOnMachineFunction(MachineFunction &MF) override;
633
634 void getAnalysisUsage(AnalysisUsage &AU) const override {
635 AU.setPreservesCFG();
636 MachineFunctionPass::getAnalysisUsage(AU);
637 }
638 StringRef getPassName() const override {
639 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
640 }
641
642private:
643 bool expandMBB(MachineBasicBlock &MBB);
644 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
645 MachineBasicBlock::iterator &NextMBBI);
646 bool expandAuipcInstPair(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator MBBI,
648 MachineBasicBlock::iterator &NextMBBI,
649 unsigned FlagsHi, unsigned SecondOpcode);
650 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
651 MachineBasicBlock::iterator MBBI,
652 MachineBasicBlock::iterator &NextMBBI);
653 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
654 MachineBasicBlock::iterator MBBI,
655 MachineBasicBlock::iterator &NextMBBI);
656 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
657 MachineBasicBlock::iterator MBBI,
658 MachineBasicBlock::iterator &NextMBBI);
659 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
660 MachineBasicBlock::iterator MBBI,
661 MachineBasicBlock::iterator &NextMBBI);
662 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
663 MachineBasicBlock::iterator MBBI,
664 MachineBasicBlock::iterator &NextMBBI);
665
666#ifndef NDEBUG
667 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
668 unsigned Size = 0;
669 for (auto &MBB : MF)
670 for (auto &MI : MBB)
671 Size += TII->getInstSizeInBytes(MI);
672 return Size;
673 }
674#endif
675};
676
677char RISCVPreRAExpandPseudo::ID = 0;
678
679bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
680 STI = &MF.getSubtarget<RISCVSubtarget>();
681 TII = STI->getInstrInfo();
682
683#ifndef NDEBUG
684 const unsigned OldSize = getInstSizeInBytes(MF);
685#endif
686
687 bool Modified = false;
688 for (auto &MBB : MF)
689 Modified |= expandMBB(MBB);
690
691#ifndef NDEBUG
692 const unsigned NewSize = getInstSizeInBytes(MF);
693 assert(OldSize >= NewSize);
694#endif
695 return Modified;
696}
697
698bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
699 bool Modified = false;
700
701 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
702 while (MBBI != E) {
703 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
704 Modified |= expandMI(MBB, MBBI, NMBBI);
705 MBBI = NMBBI;
706 }
707
708 return Modified;
709}
710
711bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
712 MachineBasicBlock::iterator MBBI,
713 MachineBasicBlock::iterator &NextMBBI) {
714
715 switch (MBBI->getOpcode()) {
716 case RISCV::PseudoLLA:
717 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
718 case RISCV::PseudoLGA:
719 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
720 case RISCV::PseudoLA_TLS_IE:
721 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
722 case RISCV::PseudoLA_TLS_GD:
723 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
724 case RISCV::PseudoLA_TLSDESC:
725 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
726 }
727 return false;
728}
729
730bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
731 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
732 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
733 unsigned SecondOpcode) {
734 MachineFunction *MF = MBB.getParent();
735 MachineInstr &MI = *MBBI;
736 DebugLoc DL = MI.getDebugLoc();
737
738 Register DestReg = MI.getOperand(0).getReg();
739 Register ScratchReg =
740 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
741
742 MachineOperand &Symbol = MI.getOperand(1);
743 Symbol.setTargetFlags(FlagsHi);
744 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
745
746 MachineInstr *MIAUIPC =
747 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
748 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
749
750 MachineInstr *SecondMI =
751 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
752 .addReg(ScratchReg)
753 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
754
755 if (MI.hasOneMemOperand())
756 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
757
758 MI.eraseFromParent();
759 return true;
760}
761
762bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
763 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
764 MachineBasicBlock::iterator &NextMBBI) {
765 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
766 RISCV::ADDI);
767}
768
769bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
770 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
771 MachineBasicBlock::iterator &NextMBBI) {
772 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
773 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
774 SecondOpcode);
775}
776
777bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
778 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
779 MachineBasicBlock::iterator &NextMBBI) {
780 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
781 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
782 SecondOpcode);
783}
784
785bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
786 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
787 MachineBasicBlock::iterator &NextMBBI) {
788 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
789 RISCV::ADDI);
790}
791
792bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
793 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
794 MachineBasicBlock::iterator &NextMBBI) {
795 MachineFunction *MF = MBB.getParent();
796 MachineInstr &MI = *MBBI;
797 DebugLoc DL = MI.getDebugLoc();
798
799 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
800 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
801
802 Register FinalReg = MI.getOperand(0).getReg();
803 Register DestReg =
804 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
805 Register ScratchReg =
806 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
807
808 MachineOperand &Symbol = MI.getOperand(1);
809 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
810 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
811
812 MachineInstr *MIAUIPC =
813 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
814 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
815
816 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
817 .addReg(ScratchReg)
818 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
819
820 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
821 .addReg(ScratchReg)
822 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
823
824 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
825 .addReg(DestReg)
826 .addImm(0)
827 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
828
829 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
830 .addReg(RISCV::X10)
831 .addReg(RISCV::X4);
832
833 MI.eraseFromParent();
834 return true;
835}
836
837} // end of anonymous namespace
838
839INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
840 RISCV_EXPAND_PSEUDO_NAME, false, false)
841
842INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
843 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
844
845namespace llvm {
846
847FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
848FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
849
850} // end of namespace llvm
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2127
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:26
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition SystemZLongBranch.cpp:211
RHS
Value * RHS
Definition X86PartialReduction.cpp:81
LHS
Value * LHS
Definition X86PartialReduction.cpp:80
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:75
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:270
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:123
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
LLVM_ABI MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition MCContext.cpp:395
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:199
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:944
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:825
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1161
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:346
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:188
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:794
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:543
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition MachineFunction.h:741
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:804
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:506
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1043
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:310
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition MachineInstrBuilder.h:373
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:248
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:218
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:73
llvm::MachineInstr::setPreInstrSymbol
LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition MachineInstr.cpp:480
llvm::MachineInstr::addMemOperand
LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition MachineInstr.cpp:385
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:154
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition RISCVSubtarget.h:143
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition RISCVSubtarget.h:142
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:419
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1205
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:242
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
INITIALIZE_PASS
TargetPassConfig.
Definition TargetPassConfig.cpp:391
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:139
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:366
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:532
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:165
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:65
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:57
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:24
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:847
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:848
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