#include "Target/RISCV/RISCVSubtarget.h"

Inheritance diagram for llvm::RISCVSubtarget:

Public Types
enum	RISCVProcFamilyEnum : uint8_t { Others , SiFive7 , VentanaVeyron , MIPSP8700 , Andes45 }
enum	RISCVVRGatherCostModelEnum : uint8_t { Quadratic , NLog2N }

Public Member Functions
	RISCVSubtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
	~RISCVSubtarget () override
void	ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVFrameLowering *	getFrameLowering () const override
const RISCVInstrInfo *	getInstrInfo () const override
const RISCVRegisterInfo *	getRegisterInfo () const override
const RISCVTargetLowering *	getTargetLowering () const override
bool	enableMachineScheduler () const override
bool	enablePostRAScheduler () const override
Align	getPrefFunctionAlignment () const
Align	getPrefLoopAlignment () const
RISCVProcFamilyEnum	getProcFamily () const
	Returns RISC-V processor family.
RISCVVRGatherCostModelEnum	getVRGatherCostModel () const
bool	hasStdExtCOrZca () const
bool	hasStdExtCOrZcd () const
bool	hasStdExtCOrZcfOrZce () const
bool	hasStdExtZvl () const
bool	hasStdExtFOrZfinx () const
bool	hasStdExtDOrZdinx () const
bool	hasStdExtZfhOrZhinx () const
bool	hasStdExtZfhminOrZhinxmin () const
bool	hasHalfFPLoadStoreMove () const
bool	hasCLZLike () const
bool	hasCTZLike () const
bool	hasCPOPLike () const
bool	hasREV8Like () const
bool	hasBEXTILike () const
bool	hasCZEROLike () const
bool	hasConditionalMoveFusion () const
bool	hasShlAdd (int64_t ShAmt) const
bool	is64Bit () const
bool	isLittleEndian () const
MVT	getXLenVT () const
unsigned	getXLen () const
bool	useMIPSLoadStorePairs () const
bool	useMIPSCCMovInsn () const
unsigned	getFLen () const
Align	getZilsdAlign () const
unsigned	getELen () const
unsigned	getRealMinVLen () const
unsigned	getRealMaxVLen () const
std::optional< unsigned >	getRealVLen () const
template<typename Quantity>
Quantity	expandVScale (Quantity X) const
	If the ElementCount or TypeSize `X` is scalable and VScale (VLEN) is exactly known, returns `X` converted to a fixed quantity.
RISCVABI::ABI	getTargetABI () const
bool	isSoftFPABI () const
bool	isRegisterReservedByUser (Register i) const override
bool	isXRaySupported () const override
bool	hasVInstructions () const
bool	hasVInstructionsI64 () const
bool	hasVInstructionsF16Minimal () const
bool	hasVInstructionsF16 () const
bool	hasVInstructionsBF16Minimal () const
bool	hasVInstructionsF32 () const
bool	hasVInstructionsF64 () const
bool	hasVInstructionsBF16 () const
bool	hasVInstructionsAnyF () const
bool	hasVInstructionsFullMultiply () const
unsigned	getMaxInterleaveFactor () const
bool	hasOptimizedSegmentLoadStore (unsigned NF) const
bool	enablePExtSIMDCodeGen () const
unsigned	getDLenFactor () const
const SelectionDAGTargetInfo *	getSelectionDAGInfo () const override
const CallLowering *	getCallLowering () const override
InstructionSelector *	getInstructionSelector () const override
const LegalizerInfo *	getLegalizerInfo () const override
const RISCVRegisterBankInfo *	getRegBankInfo () const override
bool	isTargetAndroid () const
bool	isTargetFuchsia () const
bool	useConstantPoolForLargeInts () const
unsigned	getMaxBuildIntsCost () const
unsigned	getMaxLMULForFixedLengthVectors () const
bool	useRVVForFixedLengthVectors () const
bool	enableSubRegLiveness () const override
bool	enableMachinePipeliner () const override
bool	useDFAforSMS () const override
bool	useAA () const override
	Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
unsigned	getCacheLineSize () const override
unsigned	getPrefetchDistance () const override
unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
unsigned	getMaxPrefetchIterationsAhead () const override
bool	enableWritePrefetching () const override
unsigned	getMinimumJumpTableEntries () const
unsigned	getTailDupAggressiveThreshold () const
unsigned	getMaxStoresPerMemset (bool OptSize) const
unsigned	getMaxGluedStoresPerMemcpy () const
unsigned	getMaxStoresPerMemcpy (bool OptSize) const
unsigned	getMaxStoresPerMemmove (bool OptSize) const
unsigned	getMaxLoadsPerMemcmp (bool OptSize) const
MISched::Direction	getPostRASchedDirection () const
void	overrideSchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const override
void	overridePostRASchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const override

Protected Member Functions
unsigned	getMaxRVVVectorSizeInBits () const
unsigned	getMinRVVVectorSizeInBits () const

Protected Attributes
std::unique_ptr< const SelectionDAGTargetInfo >	TSInfo
std::unique_ptr< CallLowering >	CallLoweringInfo
std::unique_ptr< InstructionSelector >	InstSelector
std::unique_ptr< LegalizerInfo >	Legalizer
std::unique_ptr< RISCVRegisterBankInfo >	RegBankInfo

Detailed Description

Definition at line 79 of file RISCVSubtarget.h.

Member Enumeration Documentation

◆ RISCVProcFamilyEnum

enum llvm::RISCVSubtarget::RISCVProcFamilyEnum : uint8_t

Enumerator
Others
SiFive7
VentanaVeyron
MIPSP8700
Andes45

Definition at line 82 of file RISCVSubtarget.h.

◆ RISCVVRGatherCostModelEnum

enum llvm::RISCVSubtarget::RISCVVRGatherCostModelEnum : uint8_t

Enumerator
Quadratic
NLog2N

Definition at line 89 of file RISCVSubtarget.h.

Constructor & Destructor Documentation

◆ RISCVSubtarget()

RISCVSubtarget::RISCVSubtarget	(	const Triple &	TT,
		StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS,
		StringRef	ABIName,
		unsigned	RVVVectorBitsMin,
		unsigned	RVVVectorLMULMax,
		const TargetMachine &	TM )

Definition at line 106 of file RISCVSubtarget.cpp.

References isLittleEndian(), and TSInfo.

◆ ~RISCVSubtarget()

RISCVSubtarget::~RISCVSubtarget ( )

overridedefault

Member Function Documentation

◆ enableMachinePipeliner()

bool RISCVSubtarget::enableMachinePipeliner ( ) const

override

Definition at line 217 of file RISCVSubtarget.cpp.

◆ enableMachineScheduler()

bool llvm::RISCVSubtarget::enableMachineScheduler ( ) const

inlineoverride

Definition at line 150 of file RISCVSubtarget.h.

◆ enablePExtSIMDCodeGen()

bool RISCVSubtarget::enablePExtSIMDCodeGen ( ) const

Definition at line 157 of file RISCVSubtarget.cpp.

References EnablePExtSIMDCodeGen.

Referenced by lowerBUILD_VECTOR(), and performTRUNCATECombine().

◆ enablePostRAScheduler()

bool llvm::RISCVSubtarget::enablePostRAScheduler ( ) const

inlineoverride

Definition at line 152 of file RISCVSubtarget.h.

◆ enableSubRegLiveness()

bool RISCVSubtarget::enableSubRegLiveness ( ) const

override

Definition at line 215 of file RISCVSubtarget.cpp.

◆ enableWritePrefetching()

bool llvm::RISCVSubtarget::enableWritePrefetching ( ) const

inlineoverride

Definition at line 403 of file RISCVSubtarget.h.

◆ expandVScale()

template<typename Quantity>

Quantity llvm::RISCVSubtarget::expandVScale ( Quantity X ) const

inline

If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted to a fixed quantity.

Otherwise returns X unmodified.

Definition at line 273 of file RISCVSubtarget.h.

References getRealVLen(), llvm::RISCV::RVVBitsPerBlock, and X.

◆ getCacheLineSize()

unsigned llvm::RISCVSubtarget::getCacheLineSize ( ) const

inlineoverride

Definition at line 388 of file RISCVSubtarget.h.

◆ getCallLowering()

const CallLowering * RISCVSubtarget::getCallLowering ( ) const

override

Definition at line 126 of file RISCVSubtarget.cpp.

References CallLoweringInfo, and getTargetLowering().

◆ getDLenFactor()

unsigned llvm::RISCVSubtarget::getDLenFactor ( ) const

inline

Definition at line 338 of file RISCVSubtarget.h.

◆ getELen()

unsigned llvm::RISCVSubtarget::getELen ( ) const

inline

Definition at line 250 of file RISCVSubtarget.h.

References assert(), hasVInstructions(), and hasVInstructionsI64().

Referenced by combineBinOpOfExtractToReduceTree(), getContainerForFixedLengthVector(), getWideningInterleave(), isInterleaveShuffle(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), lowerGetVectorLength(), lowerVECTOR_SHUFFLE(), performVECTOR_SHUFFLECombine(), and useRVVForFixedLengthVectorVT().

◆ getFLen()

unsigned llvm::RISCVSubtarget::getFLen ( ) const

inline

Definition at line 234 of file RISCVSubtarget.h.

Referenced by lowerBUILD_VECTOR().

◆ getFrameLowering()

const RISCVFrameLowering * llvm::RISCVSubtarget::getFrameLowering ( ) const

inlineoverride

Definition at line 139 of file RISCVSubtarget.h.

Referenced by llvm::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo().

◆ getInstrInfo()

const RISCVInstrInfo * llvm::RISCVSubtarget::getInstrInfo ( ) const

inlineoverride

Definition at line 142 of file RISCVSubtarget.h.

Referenced by emitFROUND(), EmitLoweredCascadedSelect(), emitSelectPseudo(), llvm::RISCVCallLowering::lowerCall(), lowerRISCVVMachineInstrToMCInst(), and llvm::RISCVRegisterInfo::lowerSegmentSpillReload().

◆ getInstructionSelector()

InstructionSelector * RISCVSubtarget::getInstructionSelector ( ) const

override

Definition at line 132 of file RISCVSubtarget.cpp.

References llvm::createRISCVInstructionSelector(), getRegBankInfo(), and InstSelector.

◆ getLegalizerInfo()

const LegalizerInfo * RISCVSubtarget::getLegalizerInfo ( ) const

override

Definition at line 141 of file RISCVSubtarget.cpp.

References Legalizer.

◆ getMaxBuildIntsCost()

unsigned RISCVSubtarget::getMaxBuildIntsCost ( ) const

Definition at line 161 of file RISCVSubtarget.cpp.

References RISCVMaxBuildIntsCost.

Referenced by lowerConstant().

◆ getMaxGluedStoresPerMemcpy()

unsigned llvm::RISCVSubtarget::getMaxGluedStoresPerMemcpy ( ) const

inline

Definition at line 416 of file RISCVSubtarget.h.

◆ getMaxInterleaveFactor()

unsigned llvm::RISCVSubtarget::getMaxInterleaveFactor ( ) const

inline

Definition at line 309 of file RISCVSubtarget.h.

References hasVInstructions().

◆ getMaxLMULForFixedLengthVectors()

unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors ( ) const

Definition at line 201 of file RISCVSubtarget.cpp.

References assert(), llvm::bit_floor(), llvm::has_single_bit(), hasVInstructions(), and RVVVectorLMULMax.

Referenced by combineVectorSizedSetCCEquality(), and useRVVForFixedLengthVectorVT().

◆ getMaxLoadsPerMemcmp()

unsigned llvm::RISCVSubtarget::getMaxLoadsPerMemcmp ( bool OptSize ) const

inline

Definition at line 430 of file RISCVSubtarget.h.

◆ getMaxPrefetchIterationsAhead()

unsigned llvm::RISCVSubtarget::getMaxPrefetchIterationsAhead ( ) const

inlineoverride

Definition at line 400 of file RISCVSubtarget.h.

◆ getMaxRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits ( ) const

protected

Definition at line 172 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMaxVLen().

◆ getMaxStoresPerMemcpy()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemcpy ( bool OptSize ) const

inline

Definition at line 420 of file RISCVSubtarget.h.

◆ getMaxStoresPerMemmove()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemmove ( bool OptSize ) const

inline

Definition at line 425 of file RISCVSubtarget.h.

◆ getMaxStoresPerMemset()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemset ( bool OptSize ) const

inline

Definition at line 411 of file RISCVSubtarget.h.

◆ getMinimumJumpTableEntries()

unsigned RISCVSubtarget::getMinimumJumpTableEntries ( ) const

Definition at line 225 of file RISCVSubtarget.cpp.

References RISCVMinimumJumpTableEntries.

◆ getMinPrefetchStride()

unsigned llvm::RISCVSubtarget::getMinPrefetchStride	(	unsigned	NumMemAccesses,
		unsigned	NumStridedMemAccesses,
		unsigned	NumPrefetches,
		bool	HasCall ) const

inlineoverride

Definition at line 394 of file RISCVSubtarget.h.

◆ getMinRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMinRVVVectorSizeInBits ( ) const

protected

Definition at line 185 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMinVLen(), and useRVVForFixedLengthVectors().

◆ getPostRASchedDirection()

MISched::Direction llvm::RISCVSubtarget::getPostRASchedDirection ( ) const

inline

Definition at line 435 of file RISCVSubtarget.h.

Referenced by overridePostRASchedPolicy().

◆ getPrefetchDistance()

unsigned llvm::RISCVSubtarget::getPrefetchDistance ( ) const

inlineoverride

Definition at line 391 of file RISCVSubtarget.h.

◆ getPrefFunctionAlignment()

Align llvm::RISCVSubtarget::getPrefFunctionAlignment ( ) const

inline

Definition at line 154 of file RISCVSubtarget.h.

◆ getPrefLoopAlignment()

Align llvm::RISCVSubtarget::getPrefLoopAlignment ( ) const

inline

Definition at line 157 of file RISCVSubtarget.h.

◆ getProcFamily()

RISCVProcFamilyEnum llvm::RISCVSubtarget::getProcFamily ( ) const

inline

Returns RISC-V processor family.

Avoid this function! CPU specifics should be kept local to this class and preferably modeled with SubtargetFeatures or properties in initializeProperties().

Definition at line 165 of file RISCVSubtarget.h.

◆ getRealMaxVLen()

unsigned llvm::RISCVSubtarget::getRealMaxVLen ( ) const

inline

Definition at line 258 of file RISCVSubtarget.h.

References getMaxRVVVectorSizeInBits().

Referenced by combineToVCPOP(), and getRealVLen().

◆ getRealMinVLen()

unsigned llvm::RISCVSubtarget::getRealMinVLen ( ) const

inline

Definition at line 254 of file RISCVSubtarget.h.

References getMinRVVVectorSizeInBits().

Referenced by combineVectorSizedSetCCEquality(), getContainerForFixedLengthVector(), getRealVLen(), getSmallestVTForIndex(), isValidEGW(), lowerBuildVectorOfConstants(), lowerVECTOR_SHUFFLE(), and useRVVForFixedLengthVectorVT().

◆ getRealVLen()

std::optional< unsigned > llvm::RISCVSubtarget::getRealVLen ( ) const

inline

Definition at line 263 of file RISCVSubtarget.h.

References getRealMaxVLen(), and getRealMinVLen().

Referenced by expandVScale(), lowerBUILD_VECTOR(), llvm::RISCVRegisterInfo::lowerSegmentSpillReload(), lowerShuffleViaVRegSplitting(), and lowerVECTOR_SHUFFLE().

◆ getRegBankInfo()

const RISCVRegisterBankInfo * RISCVSubtarget::getRegBankInfo ( ) const

override

Definition at line 147 of file RISCVSubtarget.cpp.

References RegBankInfo.

Referenced by getInstructionSelector(), and llvm::RISCVCallLowering::lowerCall().

◆ getRegisterInfo()

const RISCVRegisterInfo * llvm::RISCVSubtarget::getRegisterInfo ( ) const

inlineoverride

Definition at line 143 of file RISCVSubtarget.h.

Referenced by isConvertibleToVMV_V_V(), llvm::RISCVCallLowering::lowerCall(), lowerRISCVVMachineInstrToMCInst(), llvm::RISCVRegisterInfo::lowerSegmentSpillReload(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

◆ getSelectionDAGInfo()

const SelectionDAGTargetInfo * RISCVSubtarget::getSelectionDAGInfo ( ) const

override

Definition at line 122 of file RISCVSubtarget.cpp.

References TSInfo.

◆ getTailDupAggressiveThreshold()

unsigned llvm::RISCVSubtarget::getTailDupAggressiveThreshold ( ) const

inline

Definition at line 407 of file RISCVSubtarget.h.

◆ getTargetABI()

RISCVABI::ABI llvm::RISCVSubtarget::getTargetABI ( ) const

inline

Definition at line 281 of file RISCVSubtarget.h.

Referenced by llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), and CC_RISCVAssign2XLen().

◆ getTargetLowering()

const RISCVTargetLowering * llvm::RISCVSubtarget::getTargetLowering ( ) const

inlineoverride

Definition at line 146 of file RISCVSubtarget.h.

Referenced by llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), getCallLowering(), isLegalBitRotate(), and lowerBitreverseShuffle().

◆ getVRGatherCostModel()

RISCVVRGatherCostModelEnum llvm::RISCVSubtarget::getVRGatherCostModel ( ) const

inline

Definition at line 167 of file RISCVSubtarget.h.

◆ getXLen()

unsigned llvm::RISCVSubtarget::getXLen ( ) const

inline

Definition at line 229 of file RISCVSubtarget.h.

References is64Bit().

Referenced by llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), combineSelectAndUse(), combineVectorSizedSetCCEquality(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), lowerFABSorFNEG(), lowerFCOPYSIGN(), performBITREVERSECombine(), transformAddImmMulImm(), and transformAddShlImm().

◆ getXLenVT()

MVT llvm::RISCVSubtarget::getXLenVT ( ) const

inline

Definition at line 226 of file RISCVSubtarget.h.

References is64Bit().

Referenced by buildDefaultVLOps(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), combine_CC(), combineShlAddIAdd(), combineSubShiftToOrcB(), combineToVCPOP(), combineVectorSizedSetCCEquality(), expandMul(), getDefaultScalableVLOps(), getDefaultVLOps(), getVSlidedown(), getVSlideup(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), lowerCttzElts(), lowerDisjointIndicesShuffle(), lowerFABSorFNEG(), lowerFCOPYSIGN(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerGetVectorLength(), lowerReductionSeq(), lowerScalarInsert(), lowerScalarSplat(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), lowerVZIP(), matchSplatAsGather(), performCONCAT_VECTORSCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performSRACombine(), performVECTOR_SHUFFLECombine(), performVP_REVERSECombine(), performVP_STORECombine(), promoteVCIXScalar(), selectVSplatImmHelper(), and tryMemPairCombine().

◆ getZilsdAlign()

Align llvm::RISCVSubtarget::getZilsdAlign ( ) const

inline

Definition at line 244 of file RISCVSubtarget.h.

◆ hasBEXTILike()

bool llvm::RISCVSubtarget::hasBEXTILike ( ) const

inline

Definition at line 204 of file RISCVSubtarget.h.

Referenced by useInversedSetcc().

◆ hasCLZLike()

bool llvm::RISCVSubtarget::hasCLZLike ( ) const

inline

Definition at line 190 of file RISCVSubtarget.h.

◆ hasConditionalMoveFusion()

bool llvm::RISCVSubtarget::hasConditionalMoveFusion ( ) const

inline

Definition at line 210 of file RISCVSubtarget.h.

Referenced by combineSelectAndUse(), lowerSelectToBinOp(), and performSELECTCombine().

◆ hasCPOPLike()

bool llvm::RISCVSubtarget::hasCPOPLike ( ) const

inline

Definition at line 197 of file RISCVSubtarget.h.

◆ hasCTZLike()

bool llvm::RISCVSubtarget::hasCTZLike ( ) const

inline

Definition at line 194 of file RISCVSubtarget.h.

◆ hasCZEROLike()

bool llvm::RISCVSubtarget::hasCZEROLike ( ) const

inline

Definition at line 206 of file RISCVSubtarget.h.

Referenced by combineANDOfSETCCToCZERO(), combineSelectAndUse(), lowerSelectToBinOp(), and useInversedSetcc().

◆ hasHalfFPLoadStoreMove()

bool llvm::RISCVSubtarget::hasHalfFPLoadStoreMove ( ) const

inline

Definition at line 186 of file RISCVSubtarget.h.

◆ hasOptimizedSegmentLoadStore()

bool llvm::RISCVSubtarget::hasOptimizedSegmentLoadStore ( unsigned NF ) const

inline

Definition at line 313 of file RISCVSubtarget.h.

References llvm_unreachable.

◆ hasREV8Like()

bool llvm::RISCVSubtarget::hasREV8Like ( ) const

inline

Definition at line 200 of file RISCVSubtarget.h.

◆ hasShlAdd()

bool llvm::RISCVSubtarget::hasShlAdd ( int64_t ShAmt ) const

inline

Definition at line 216 of file RISCVSubtarget.h.

Referenced by combineShlAddIAdd(), expandMul(), isWorthFoldingIntoRegRegScale(), lowerSelectToBinOp(), and transformAddShlImm().

◆ hasStdExtCOrZca()

bool llvm::RISCVSubtarget::hasStdExtCOrZca ( ) const

inline

Definition at line 174 of file RISCVSubtarget.h.

References hasStdExtCOrZca().

Referenced by hasStdExtCOrZca().

◆ hasStdExtCOrZcd()

bool llvm::RISCVSubtarget::hasStdExtCOrZcd ( ) const

inline

Definition at line 175 of file RISCVSubtarget.h.

Referenced by isCompressibleLoad(), and isCompressibleStore().

◆ hasStdExtCOrZcfOrZce()

bool llvm::RISCVSubtarget::hasStdExtCOrZcfOrZce ( ) const

inline

Definition at line 176 of file RISCVSubtarget.h.

Referenced by isCompressibleLoad(), and isCompressibleStore().

◆ hasStdExtDOrZdinx()

bool llvm::RISCVSubtarget::hasStdExtDOrZdinx ( ) const

inline

Definition at line 181 of file RISCVSubtarget.h.

◆ hasStdExtFOrZfinx()

bool llvm::RISCVSubtarget::hasStdExtFOrZfinx ( ) const

inline

Definition at line 180 of file RISCVSubtarget.h.

◆ hasStdExtZfhminOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZfhminOrZhinxmin ( ) const

inline

Definition at line 183 of file RISCVSubtarget.h.

◆ hasStdExtZfhOrZhinx()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZhinx ( ) const

inline

Definition at line 182 of file RISCVSubtarget.h.

Referenced by lowerFP_TO_INT(), lowerFP_TO_INT_SAT(), and lowerINT_TO_FP().

◆ hasStdExtZvl()

bool llvm::RISCVSubtarget::hasStdExtZvl ( ) const

inline

Definition at line 179 of file RISCVSubtarget.h.

◆ hasVInstructions()

bool llvm::RISCVSubtarget::hasVInstructions ( ) const

inline

Definition at line 296 of file RISCVSubtarget.h.

Referenced by combineBinOpOfExtractToReduceTree(), combineVectorSizedSetCCEquality(), getELen(), getMaxInterleaveFactor(), getMaxLMULForFixedLengthVectors(), getMaxRVVVectorSizeInBits(), getMinRVVVectorSizeInBits(), getScavSlotsNumForRVV(), isSupportedArgumentType(), isSupportedReturnType(), lowerVectorIntrinsicScalars(), reverseZExtICmpCombine(), and useRVVForFixedLengthVectors().

◆ hasVInstructionsAnyF()

bool llvm::RISCVSubtarget::hasVInstructionsAnyF ( ) const

inline

Definition at line 307 of file RISCVSubtarget.h.

References hasVInstructionsF32().

◆ hasVInstructionsBF16()

bool llvm::RISCVSubtarget::hasVInstructionsBF16 ( ) const

inline

Definition at line 305 of file RISCVSubtarget.h.

Referenced by isPromotedOpNeedingSplit(), lowerBUILD_VECTOR(), and lowerScalarSplat().

◆ hasVInstructionsBF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsBF16Minimal ( ) const

inline

Definition at line 300 of file RISCVSubtarget.h.

Referenced by isLegalElementTypeForRVV(), isPromotedOpNeedingSplit(), and useRVVForFixedLengthVectorVT().

◆ hasVInstructionsF16()

bool llvm::RISCVSubtarget::hasVInstructionsF16 ( ) const

inline

Definition at line 299 of file RISCVSubtarget.h.

Referenced by isPromotedOpNeedingSplit(), and lowerVECTOR_SHUFFLEAsVSlide1().

◆ hasVInstructionsF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsF16Minimal ( ) const

inline

Definition at line 298 of file RISCVSubtarget.h.

Referenced by isLegalElementTypeForRVV(), isPromotedOpNeedingSplit(), and useRVVForFixedLengthVectorVT().

◆ hasVInstructionsF32()

bool llvm::RISCVSubtarget::hasVInstructionsF32 ( ) const

inline

Definition at line 303 of file RISCVSubtarget.h.

Referenced by hasVInstructionsAnyF(), isLegalElementTypeForRVV(), and useRVVForFixedLengthVectorVT().

◆ hasVInstructionsF64()

bool llvm::RISCVSubtarget::hasVInstructionsF64 ( ) const

inline

Definition at line 304 of file RISCVSubtarget.h.

Referenced by isLegalElementTypeForRVV(), and useRVVForFixedLengthVectorVT().

◆ hasVInstructionsFullMultiply()

bool llvm::RISCVSubtarget::hasVInstructionsFullMultiply ( ) const

inline

Definition at line 308 of file RISCVSubtarget.h.

◆ hasVInstructionsI64()

bool llvm::RISCVSubtarget::hasVInstructionsI64 ( ) const

inline

Definition at line 297 of file RISCVSubtarget.h.

Referenced by getELen(), isLegalElementTypeForRVV(), and useRVVForFixedLengthVectorVT().

◆ is64Bit()

bool llvm::RISCVSubtarget::is64Bit ( ) const

inline

Definition at line 224 of file RISCVSubtarget.h.

Referenced by llvm::CC_RISCV_FastCC(), llvm::CC_RISCV_GHC(), emitFROUND(), getPACKOpcode(), getXLen(), getXLenVT(), isCompressibleLoad(), isCompressibleStore(), isLegalElementTypeForRVV(), lowerBuildVectorOfConstants(), performANDCombine(), performSETCCCombine(), performSIGN_EXTEND_INREGCombine(), performTRUNCATECombine(), performXORCombine(), and selectConstantAddr().

◆ isLittleEndian()

bool llvm::RISCVSubtarget::isLittleEndian ( ) const

inline

Definition at line 225 of file RISCVSubtarget.h.

Referenced by emitBuildPairF64Pseudo(), emitSplitF64Pseudo(), RISCVSubtarget(), and unpackF64OnRV32DSoftABI().

◆ isRegisterReservedByUser()

bool llvm::RISCVSubtarget::isRegisterReservedByUser ( Register i ) const

inlineoverride

Definition at line 287 of file RISCVSubtarget.h.

References assert(), and llvm::Register::id().

◆ isSoftFPABI()

bool llvm::RISCVSubtarget::isSoftFPABI ( ) const

inline

Definition at line 282 of file RISCVSubtarget.h.

References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32E, and llvm::RISCVABI::ABI_LP64.

◆ isTargetAndroid()

bool llvm::RISCVSubtarget::isTargetAndroid ( ) const

inline

Definition at line 368 of file RISCVSubtarget.h.

◆ isTargetFuchsia()

bool llvm::RISCVSubtarget::isTargetFuchsia ( ) const

inline

Definition at line 369 of file RISCVSubtarget.h.

◆ isXRaySupported()

bool llvm::RISCVSubtarget::isXRaySupported ( ) const

inlineoverride

Definition at line 293 of file RISCVSubtarget.h.

◆ overridePostRASchedPolicy()

void RISCVSubtarget::overridePostRASchedPolicy	(	MachineSchedPolicy &	Policy,
		const SchedRegion &	Region ) const

override

Definition at line 247 of file RISCVSubtarget.cpp.

References llvm::MISched::Bidirectional, llvm::MISched::BottomUp, getPostRASchedDirection(), llvm::MachineSchedPolicy::OnlyBottomUp, llvm::MachineSchedPolicy::OnlyTopDown, and llvm::MISched::TopDown.

◆ overrideSchedPolicy()

void RISCVSubtarget::overrideSchedPolicy	(	MachineSchedPolicy &	Policy,
		const SchedRegion &	Region ) const

override

Definition at line 231 of file RISCVSubtarget.cpp.

References llvm::MachineSchedPolicy::DisableLatencyHeuristic, llvm::MachineSchedPolicy::OnlyBottomUp, llvm::MachineSchedPolicy::OnlyTopDown, and llvm::MachineSchedPolicy::ShouldTrackPressure.

◆ ParseSubtargetFeatures()

void llvm::RISCVSubtarget::ParseSubtargetFeatures	(	StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS )

◆ useAA()

bool RISCVSubtarget::useAA ( ) const

override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 223 of file RISCVSubtarget.cpp.

References UseAA.

◆ useConstantPoolForLargeInts()

bool RISCVSubtarget::useConstantPoolForLargeInts ( ) const

Definition at line 153 of file RISCVSubtarget.cpp.

References RISCVDisableUsingConstantPoolForLargeInts.

Referenced by lowerConstant().

◆ useDFAforSMS()

bool llvm::RISCVSubtarget::useDFAforSMS ( ) const

inlineoverride

Definition at line 384 of file RISCVSubtarget.h.

◆ useMIPSCCMovInsn()

bool RISCVSubtarget::useMIPSCCMovInsn ( ) const

Definition at line 266 of file RISCVSubtarget.cpp.

References UseMIPSCCMovInsn.

◆ useMIPSLoadStorePairs()

bool RISCVSubtarget::useMIPSLoadStorePairs ( ) const

Definition at line 262 of file RISCVSubtarget.cpp.

References UseMIPSLoadStorePairsOpt.

◆ useRVVForFixedLengthVectors()

bool RISCVSubtarget::useRVVForFixedLengthVectors ( ) const

Definition at line 210 of file RISCVSubtarget.cpp.

References getMinRVVVectorSizeInBits(), hasVInstructions(), and llvm::RISCV::RVVBitsPerBlock.

Referenced by useRVVForFixedLengthVectorVT().

Member Data Documentation

◆ CallLoweringInfo

std::unique_ptr<CallLowering> llvm::RISCVSubtarget::CallLoweringInfo

mutableprotected

Definition at line 349 of file RISCVSubtarget.h.

Referenced by getCallLowering().

◆ InstSelector

std::unique_ptr<InstructionSelector> llvm::RISCVSubtarget::InstSelector

mutableprotected

Definition at line 350 of file RISCVSubtarget.h.

Referenced by getInstructionSelector().

◆ Legalizer

std::unique_ptr<LegalizerInfo> llvm::RISCVSubtarget::Legalizer

mutableprotected

Definition at line 351 of file RISCVSubtarget.h.

Referenced by getLegalizerInfo().

◆ RegBankInfo

std::unique_ptr<RISCVRegisterBankInfo> llvm::RISCVSubtarget::RegBankInfo

mutableprotected

Definition at line 352 of file RISCVSubtarget.h.

Referenced by getRegBankInfo().

◆ TSInfo

std::unique_ptr<const SelectionDAGTargetInfo> llvm::RISCVSubtarget::TSInfo

protected

Definition at line 346 of file RISCVSubtarget.h.

Referenced by getSelectionDAGInfo(), and RISCVSubtarget().

The documentation for this class was generated from the following files:

lib/Target/RISCV/RISCVSubtarget.h
lib/Target/RISCV/RISCVSubtarget.cpp

Public Types

Public Member Functions

Protected Member Functions

Protected Attributes

Detailed Description

Member Enumeration Documentation

◆ RISCVProcFamilyEnum

◆ RISCVVRGatherCostModelEnum

Constructor & Destructor Documentation

◆ RISCVSubtarget()

◆ ~RISCVSubtarget()

Member Function Documentation

◆ enableMachinePipeliner()

◆ enableMachineScheduler()

◆ enablePExtSIMDCodeGen()

◆ enablePostRAScheduler()

◆ enableSubRegLiveness()

◆ enableWritePrefetching()

◆ expandVScale()

◆ getCacheLineSize()

◆ getCallLowering()

◆ getDLenFactor()

◆ getELen()

◆ getFLen()

◆ getFrameLowering()

◆ getInstrInfo()

◆ getInstructionSelector()

◆ getLegalizerInfo()

◆ getMaxBuildIntsCost()

◆ getMaxGluedStoresPerMemcpy()

◆ getMaxInterleaveFactor()

◆ getMaxLMULForFixedLengthVectors()

◆ getMaxLoadsPerMemcmp()

◆ getMaxPrefetchIterationsAhead()

◆ getMaxRVVVectorSizeInBits()

◆ getMaxStoresPerMemcpy()

◆ getMaxStoresPerMemmove()

◆ getMaxStoresPerMemset()

◆ getMinimumJumpTableEntries()

◆ getMinPrefetchStride()

◆ getMinRVVVectorSizeInBits()

◆ getPostRASchedDirection()

◆ getPrefetchDistance()

◆ getPrefFunctionAlignment()

◆ getPrefLoopAlignment()

◆ getProcFamily()

◆ getRealMaxVLen()

◆ getRealMinVLen()

◆ getRealVLen()

◆ getRegBankInfo()

◆ getRegisterInfo()

◆ getSelectionDAGInfo()

◆ getTailDupAggressiveThreshold()

◆ getTargetABI()

◆ getTargetLowering()

◆ getVRGatherCostModel()

◆ getXLen()

◆ getXLenVT()

◆ getZilsdAlign()

◆ hasBEXTILike()

◆ hasCLZLike()

◆ hasConditionalMoveFusion()

◆ hasCPOPLike()

◆ hasCTZLike()

◆ hasCZEROLike()

◆ hasHalfFPLoadStoreMove()

◆ hasOptimizedSegmentLoadStore()

◆ hasREV8Like()

◆ hasShlAdd()

◆ hasStdExtCOrZca()

◆ hasStdExtCOrZcd()

◆ hasStdExtCOrZcfOrZce()

◆ hasStdExtDOrZdinx()

◆ hasStdExtFOrZfinx()

◆ hasStdExtZfhminOrZhinxmin()

◆ hasStdExtZfhOrZhinx()

◆ hasStdExtZvl()

◆ hasVInstructions()

◆ hasVInstructionsAnyF()

◆ hasVInstructionsBF16()