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LLVM 22.0.0git
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Functions | |
| StringRef | selectHexagonCPU (StringRef CPU) |
| FeatureBitset | completeHVXFeatures (const FeatureBitset &FB) |
| MCSubtargetInfo * | createHexagonMCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS) |
| Create a Hexagon MCSubtargetInfo instance. | |
| MCSubtargetInfo const * | getArchSubtarget (MCSubtargetInfo const *STI) |
| void | addArchSubtarget (MCSubtargetInfo const *STI, StringRef FS) |
| unsigned | GetELFFlags (const MCSubtargetInfo &STI) |
| llvm::ArrayRef< MCPhysReg > | GetVectRegRev () |
| std::optional< unsigned > | getHVXVersion (const FeatureBitset &Features) |
| unsigned | getArchVersion (const FeatureBitset &Features) |
| void llvm::Hexagon_MC::addArchSubtarget | ( | MCSubtargetInfo const * | STI, |
| StringRef | FS ) |
Definition at line 670 of file HexagonMCTargetDesc.cpp.
References assert(), llvm::StringRef::contains(), createHexagonMCSubtargetInfo(), llvm::StringRef::drop_back(), llvm::MCSubtargetInfo::getCPU(), and llvm::MCSubtargetInfo::getTargetTriple().
Referenced by createHexagonMCSubtargetInfo(), and llvm::HexagonSubtarget::HexagonSubtarget().
| FeatureBitset llvm::Hexagon_MC::completeHVXFeatures | ( | const FeatureBitset & | FB | ) |
Definition at line 543 of file HexagonMCTargetDesc.cpp.
References F, llvm::FeatureBitset::set(), and llvm::FeatureBitset::test().
Referenced by createHexagonMCSubtargetInfo(), and llvm::HexagonSubtarget::initializeSubtargetDependencies().
| MCSubtargetInfo * llvm::Hexagon_MC::createHexagonMCSubtargetInfo | ( | const Triple & | TT, |
| StringRef | CPU, | ||
| StringRef | FS ) |
Create a Hexagon MCSubtargetInfo instance.
This is exposed so Asm parser, etc. do not need to go through TargetRegistry.
Definition at line 621 of file HexagonMCTargetDesc.cpp.
References addArchSubtarget(), checkFeature(), completeHVXFeatures(), llvm::StringRef::contains(), llvm::errs(), llvm::HexagonDisableDuplex, isCPUValid(), llvm::FeatureBitset::reset(), llvm::FeatureBitset::set(), llvm::StringRef::str(), and X.
Referenced by addArchSubtarget(), and LLVMInitializeHexagonTargetMC().
| MCSubtargetInfo const * llvm::Hexagon_MC::getArchSubtarget | ( | MCSubtargetInfo const * | STI | ) |
Definition at line 535 of file HexagonMCTargetDesc.cpp.
References llvm::MCSubtargetInfo::getCPU().
Referenced by llvm::HexagonMCInstrInfo::canonicalizePacket().
| unsigned llvm::Hexagon_MC::getArchVersion | ( | const FeatureBitset & | Features | ) |
Definition at line 694 of file HexagonMCTargetDesc.cpp.
References llvm_unreachable, and llvm::FeatureBitset::test().
Referenced by llvm::HexagonTargetStreamer::emitTargetAttributes().
| unsigned llvm::Hexagon_MC::GetELFFlags | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 706 of file HexagonMCTargetDesc.cpp.
References llvm::StringSwitch< T, R >::Case(), llvm::ELF::EF_HEXAGON_MACH_V5, llvm::ELF::EF_HEXAGON_MACH_V55, llvm::ELF::EF_HEXAGON_MACH_V60, llvm::ELF::EF_HEXAGON_MACH_V62, llvm::ELF::EF_HEXAGON_MACH_V65, llvm::ELF::EF_HEXAGON_MACH_V66, llvm::ELF::EF_HEXAGON_MACH_V67, llvm::ELF::EF_HEXAGON_MACH_V67T, llvm::ELF::EF_HEXAGON_MACH_V68, llvm::ELF::EF_HEXAGON_MACH_V69, llvm::ELF::EF_HEXAGON_MACH_V71, llvm::ELF::EF_HEXAGON_MACH_V71T, llvm::ELF::EF_HEXAGON_MACH_V73, llvm::ELF::EF_HEXAGON_MACH_V75, llvm::ELF::EF_HEXAGON_MACH_V79, llvm::ELF::EF_HEXAGON_MACH_V81, and llvm::MCSubtargetInfo::getCPU().
| std::optional< unsigned > llvm::Hexagon_MC::getHVXVersion | ( | const FeatureBitset & | Features | ) |
Definition at line 682 of file HexagonMCTargetDesc.cpp.
References llvm::FeatureBitset::test().
Referenced by llvm::HexagonTargetStreamer::emitTargetAttributes().
| llvm::ArrayRef< MCPhysReg > llvm::Hexagon_MC::GetVectRegRev | ( | ) |
Definition at line 727 of file HexagonMCTargetDesc.cpp.
References llvm::ArrayRef().
Referenced by llvm::HexagonRegisterInfo::getReservedRegs().
Definition at line 171 of file HexagonMCTargetDesc.cpp.
References DefaultArch, llvm::StringRef::empty(), HexagonGetArchVariant(), llvm::report_fatal_error(), and llvm::StringRef::split().
Referenced by llvm::createHexagonAsmBackend().