Enumeration Type Documentation
◆ NodeType
| enum llvm::NVPTXISD::NodeType : unsigned |
| Enumerator | |
|---|---|
| FIRST_NUMBER | |
| RET_GLUE | |
| DeclareScalarParam | These nodes represent a parameter declaration. In PTX this will look like: .param .align 16 .b8 param0[1024]; .param .b32 retval0; DeclareArrayParam(Chain, Externalsym, Align, Size, Glue) DeclareScalarParam(Chain, Externalsym, Size, Glue) |
| DeclareArrayParam | |
| CALL | This node represents a PTX call instruction. It's operands are as follows: CALL(Chain, IsConvergent, IsIndirectCall/IsUniform, NumReturns, NumParams, Callee, Proto) |
| MoveParam | |
| CallPrototype | |
| ProxyReg | |
| FSHL_CLAMP | |
| FSHR_CLAMP | |
| MUL_WIDE_SIGNED | |
| MUL_WIDE_UNSIGNED | |
| SETP_F16X2 | |
| SETP_BF16X2 | |
| BFI | |
| PRMT | |
| BUILD_VECTOR | This node is similar to ISD::BUILD_VECTOR except that the output may be implicitly bitcast to a scalar. This allows for the representation of packing move instructions for vector types which are not legal i.e. v2i32 |
| UNPACK_VECTOR | This node is the inverse of NVPTX::BUILD_VECTOR. It takes a single value which may be a scalar and unpacks it into multiple values by implicitly converting it to a vector. |
| FCOPYSIGN | |
| FMAXNUM3 | |
| FMINNUM3 | |
| FMAXIMUM3 | |
| FMINIMUM3 | |
| DYNAMIC_STACKALLOC | |
| STACKRESTORE | |
| STACKSAVE | |
| BrxStart | |
| BrxItem | |
| BrxEnd | |
| CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED | |
| CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X | |
| CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y | |
| CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z | |
| CVT_E4M3X4_F32X4_RS_SF | |
| CVT_E5M2X4_F32X4_RS_SF | |
| CVT_E2M3X4_F32X4_RS_SF | |
| CVT_E3M2X4_F32X4_RS_SF | |
| CVT_E2M1X4_F32X4_RS_SF | |
| FIRST_MEMORY_OPCODE | |
| ATOMIC_CMP_SWAP_B128 | These nodes are used to lower atomic instructions with i128 type. They are similar to the generic nodes, but the input and output values are split into two 64-bit values. ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP_B128(INCHAIN, ptr, cmpLo, cmpHi, swapLo, swapHi) ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP_B128(INCHAIN, ptr, amtLo, amtHi) |
| ATOMIC_SWAP_B128 | |
| LoadV2 | |
| LoadV4 | |
| LoadV8 | |
| LDUV2 | |
| LDUV4 | |
| StoreV2 | |
| StoreV4 | |
| StoreV8 | |
| TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1 | |
| TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2 | |
| TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1 | |
| TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2 | |
| TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1 | |
| TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2 | |
| TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1 | |
| TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2 | |
| TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT | |
| TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT | |
| TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT | |
| TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT | |
| TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1 | |
| TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2 | |
| TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1 | |
| TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2 | |
| TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1 | |
| TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2 | |
| TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT | |
| TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT | |
| TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1 | |
| TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2 | |
| TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT | |
| TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT | |
| LAST_MEMORY_OPCODE | |
Definition at line 24 of file NVPTXISelLowering.h.
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